ATtiny40 Atmel Corporation, ATtiny40 Datasheet
ATtiny40
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... Active Mode: • 200 µ MHz and 1.8V – Idle Mode: • 25 µ MHz and 1.8V – Power-down Mode: • < 0.1 µA at 1.8V ® 8-Bit Microcontroller 100 Years 8-bit Microcontroller with 4K Bytes In-System Programmable Flash ATtiny40 Preliminary Rev. 8263A–AVR–08/10 ...
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... The min- imum pulse length is given in generate a reset. The reset pin can also be used as a (weak) I/O pin. ATtiny40 2 Pinout of ATtiny40 SOIC/TSSOP (PCINT8/ADC8) PB0 1 20 (PCINT7/ADC7) PA7 ...
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... Port C has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described in The port also serves the functions of various special features of the ATtiny40, as listed on 41. 8263A–AVR–08/10 “ ...
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... Overview ATtiny40 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny40 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. DATA REGISTER ...
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... The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny40 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 8263A–AVR–08/10 ...
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... PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized. ATtiny40 6 8263A–AVR–08/10 ...
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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...
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... This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny40 8 for a detailed description. “Instruction Set Sum- “ ...
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... R27 R28 R29 R30 R31 A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny40 implements only 16 registers. For reasons of compatibility the registers are numbered R16...R31 and not R0...R15. 0 X-register Low Byte X-register High Byte Y-register Low Byte ...
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... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. ATtiny40 10 The X-, Y-, and Z-registers R27 ...
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Figure 4-4. 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-4 vard architecture and the fast access Register File concept. This is the basic pipelining concept ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny40 12 ; set Global Interrupt Enable ; enter sleep, waiting for interrupt ...
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... Hence, a stack PUSH command decreases the Stack Pointer. The stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer in ATtiny40 is implemented as two 8-bit registers in the I/O space. 8263A–AVR–08/10 7 ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR Instruction Set” and section • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and section ATtiny40 ...
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... Memories This section describes the different memories in the ATtiny40. The device has two main memory areas, the program memory space and the data memory space. 5.1 In-System Re-programmable Flash Program Memory The ATtiny40 contains 4K byte on-chip, in-system reprogrammable Flash memory for program storage ...
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... Figure 5-1. 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 5-2. ATtiny40 16 Data Memory Map (Byte Addressing) I/O SPACE SRAM DATA MEMORY (reserved) NVM LOCK BITS (reserved) ...
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Internal SRAM The internal SRAM is mapped in the Data Memory space starting at address 0x0040. SRAM is accessed from the CPU by using direct addressing, indirect addressing or via the RAM interface. The registers R26 to R31 function ...
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... I/O Memory The I/O space definition of the ATtiny40 is shown in All ATtiny40 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general purpose work- ing registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See document “ ...
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For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that CBI and ...
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... The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usu- ally active simultaneously with the CPU clock. ATtiny40 20 presents the principal clock systems and their distribution in ATtiny40. All of the “Power Management and Sleep Modes” on page Clock Distribution ANALOG-TO-DIGITAL ...
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ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.2 ...
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... The first step after the reset source has been released consists of the device counting the reset start-up time. The purpose of this reset start-up time is to ensure that supply ATtiny40 22 24. When switching between any clock sources, the clock system ensures “ ...
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The reset start-up time is counted using the inter- nal 128 kHz oscillator. See Note that the actual supply voltage is not monitored by the start-up logic. The device will count until the reset start-up ...
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... These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written at run-time to vary the clock frequency and suit the application ATtiny40 ...
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As the prescaler divides the master clock input to the MCU, the speed of all syn- chronous peripherals is reduced accordingly. The division factors are given in Table 6-4. CLKPS3 To avoid unintentional changes of clock frequency, a protected ...
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... Oscillator,” on page The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a setting of 0xFF gives the highest frequency. ATtiny40 26 Table 21-2, “Calibration Accuracy of Internal RC 167. Calibration outside the range given is not guaranteed. ...
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... Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow. If wake-up from the analog comparator interrupt is not required, the 8263A–AVR–08/10 presents the different clock systems and their distribution in ATtiny40. Active Clock Domains and Wake-up Sources in Different Sleep Modes. Active Clock Domains X 1 ...
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... Power Reduction Register The Power Reduction Register (PRR), see vides a method to reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is stopped then: ATtiny40 28 102. This will reduce power consumption in idle mode. level has dropped during the sleep period. ...
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The current state of the peripheral is frozen. • The associated registers can not be read or written. • Resources used by the peripheral will remain occupied. The peripheral should in most cases be disabled before stopping the clock. ...
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... Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1 and 0 These bits select between available sleep modes, as shown in Table 7-2. SM2 ATtiny40 input pin can cause significant current even in active mode. Digital ISC01 ISC00 – BODS ...
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Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it ...
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... This allows the power to reach a stable level before normal operation starts. The start up sequence is described in 8.2 Reset Sources The ATtiny40 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length • ...
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V V decreases below the detection level. CC Figure 8-2. V RESET TIME-OUT INTERNAL RESET Figure 8-3. V RESET TIME-OUT INTERNAL RESET 8.2.2 External Reset An External Reset is generated by a low level ...
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... CC 8.2.4 Brown-out Detection ATtiny40 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny40 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to 8263A– ...
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... Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. Write the signature for change enable of protected I/O registers to register CCP 2. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant ATtiny40 36 Watchdog Timer 128 kHz ...
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Code Examples The following code example shows how to turn off the WDT. The example assumes that inter- rupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code ...
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... The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 8-3 on page Table 8-3. WDP3 ATtiny40 38 Watchdog Timer Configuration (1) WDE WDIE Mode 0 0 Stopped 0 1 Interrupt 1 0 ...
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Table 8-3. WDP3 8.5.2 RSTFLR – Reset Flag Register The Reset Flag Register provides information on which reset source caused an MCU Reset. Bit 0x3B Read/Write Initial Value • Bits 7:4 – Res: Reserved ...
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... In case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular program code can be placed at these locations. The most typical and general setup for interrupt vector addresses in ATtiny40 is shown in the program example below. Address Labels Code ...
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External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT[17:0] pins. Observe ...
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... SLEEP command. 9.2.2 Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF ATtiny40 42 Timing of pin change interrupts pin_lat D Q pin_sync LE clk PCINT(0) in PCMSK(x) clk “Clock System” on page Figure 9-1 ...
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Register Description 9.3.1 MCUCR – MCU Control Register The MCU Control Register contains bits for controlling external interrupt sensing and power management. Bit 0x3A Read/Write Initial Value • Bits 7:6 – ISC0[1:0]: Interrupt Sense Control The External Interrupt 0 ...
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... These bits are reserved and will always read as zero. • Bit 0 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor- ATtiny40 ...
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Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. 9.3.4 ...
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... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny40 46 and Ground as indicated in Figure 10-1 on page for a complete list of parameters. ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O Pxn Note: 10.2.1 Configuring the Pin Each port pin ...
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... The Break-Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see When switching the DDRxn bit from output to input no immediate tri-state period is introduced. ATtiny40 48 summarizes the control signals for the pin value. Port Pin Configurations ...
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Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode SYSTEM CLK INSTRUCTIONS 10.2.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in ...
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... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pulldown. Connecting unused pins directly to V accidentally configured as an output. ATtiny40 50 Figure 10-5 on page 50. The out instruction sets the “SYNC LATCH” signal at the ...
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Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from input with a pull-up assigned to port pin 2. The resulting ...
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... Figure 10-6. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: Note: ATtiny40 52 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn ...
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The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microcontroller family. Some overriding signals may not be present in all port pins. Table 10-2 on page 53 indexes from signals ...
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... Analog Comparator. • PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change interrupt 0. ATtiny40 54 Port A Pins Alternate Functions Port Pin ...
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Port A, Bit 2 – ADC2/AIN1/PCINT2 • ADC2: Analog to Digital Converter, Channel 2 • AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from ...
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... AIO Note: Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny40 56 and Table 10-5 relate the alternate functions of Port A to the overriding signals Figure 10-6 on page 52. Overriding Signals for Alternate Functions in PA[7:5] PA7/ADC7/PCINT7 PCINT7 • PCIE0 + ADC7D PCINT6 • ...
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Table 10-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 10.3.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-7. • Port B, Bit 0 – ADC8/PCINT8 ...
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... DIEOE DIEOV DI AIO Table 10-9. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny40 58 and Table 10-9 on page 58 Figure 10-6 on page 52. Overriding Signals for Alternate Functions in PB[3:2] PB3/ADC11/PCINT11 PCINT11 • PCIE1 • ADC11D PCINT11 • PCIE1 PCINT11 Input ...
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Alternate Functions of Port C The Port C pins with alternate function are shown in Table 10-10. Port A Pins Alternate Functions • Port C, Bit 0 – OC0A/PCINT12 • OC0A: Output Compare Match output. Provided that the pin ...
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... CLKI: Clock Input from an external clock source, see • TPICLK: Serial Programming Clock. • PCINT17: Pin Change Interrupt source 17. The PC5 pin can serve as an external interrupt source for pin change interrupt 2. ATtiny40 60 “External Clock” on page 21. 8263A–AVR–08/10 ...
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Table 10-11 shown in Table 10-11. Overriding Signals for Alternate Functions in PC[5:3] Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Notes: 8263A–AVR–08/10 and Table 10-12 relate the alternate functions of Port C to the ...
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... Bit 1 – BBMB: Break-Before-Make Mode Enable When this bit is set the Break-Before-Make mode is activated for the entire Port B. The interme- diate tri-state cycle is then inserted when writing DDRBn to make an output. For further information, see ATtiny40 62 PC2/INT0/CLKO/MISO/ PCINT14 (1) CKOUT ...
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Bit 0 – BBMA: Break-Before-Make Mode Enable When this bit is set the Break-Before-Make mode is activated for the entire Port A. The interme- diate tri-state cycle is then inserted when writing DDRAn to make an output. For further ...
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... PORTC – Port C Data Register Bit 0x1D Read/Write Initial Value 10.4.12 DDRC – Port C Data Direction Register Bit 0x1C Read/Write Initial Value 10.4.13 PINC – Port C Input Pins Bit 0x1B Read/Write Initial Value ATtiny40 – – – – ...
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Timer/Counter0 11.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator ...
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... Timer/Counter Control Register (TCCR0B). For details on clock sources and pres- caler, see 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 11-2 on page 67 ATtiny40 66 “Output Compare Unit” on page 67 Table 11-1 are also used extensively throughout the document. Definitions ...
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Figure 11-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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... Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 ATtiny40 68 shows a block diagram of the Output Compare unit. ...
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OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting ...
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... In Clear Timer on Compare or CTC mode (WGM0[2:0] = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence ATtiny40 70 “Register Description” on page 76 ...
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This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in (TCNT0) increases until a Compare Match occurs ...
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... TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). ATtiny40 72 Figure 11-6 on page 72. The TCNT0 value is in the timing diagram ...
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The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer ...
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... The Timer/Counter is a synchronous design and the timer clock (clk clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. The figure shows the count sequence close to the MAX value in all modes other than phase cor- rect PWM mode. ATtiny40 74 Table 11-4 on page f OCnxPCPWM ...
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Figure 11-8. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOVn Figure 11-9 on page 75 Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 11-10 ...
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... When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the WGM0[2:0] bit setting. bits are set to a normal or CTC mode (non-PWM). Table 11-2. COM0A1 Table 11-3 ATtiny40 76 caler (f /8) clk_I/O TOP - 1 TOP ...
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Table 11-3. COM0A1 Note: Table 11-4 PWM mode. Table 11-4. COM0A1 Note: • Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If ...
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... Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see ATtiny40 78 shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to fast PWM mode. Compare Output Mode, Fast PWM Mode ...
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Table 11-8. Mode Note: 11.9.2 TCCR0B – Timer/Counter Control Register B Bit 0x18 Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when ...
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... The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0A pin. ATtiny40 80 “TCCR0A – Timer/Counter Control Register A” on page Clock Select Bit Description ...
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OCR0B – Output Compare Register B Bit 0x15 Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare ...
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... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM0[2:0] bit setting. See and “Waveform Generation Mode Bit Description” on page ATtiny40 82 Table 11-8 on page 79 79. 8263A–AVR–08/10 ...
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Timer/Counter1 12.1 Features • Clear Timer on Compare Match (Auto Reload) • One Input Capture unit • Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, ICF1) • 8-bit Mode with Two Independent Output Compare Units • 16-bit Mode with One ...
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... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 12-2 shows a block diagram of the counter and its surroundings. Table 12-2. ATtiny40 84 must be followed. Table 11-1 are also used extensively throughout the document. Definitions Description The counter reaches BOTTOM when it becomes 0x00 ...
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Signal description (internal signals): count clk top The counter is incremented at each timer clock (clk restarts from BOTTOM. The counting sequence is determined by the setting of the CTC1 bit located in the Timer/Counter Control Register (TCCR1A). For more ...
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... Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the trigger edge change is not required (if an interrupt handler is used). ATtiny40 86 94). The edge detector is also identical. However, when the noise canceler is (Fig- 8263A– ...
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Output Compare Unit The comparator continuously compares Timer/Counter (TCNT1) with the Output Compare Reg- isters (OCR1A and OCR1B), and whenever the Timer/Counter equals to the Output Compare Regisers, the comparator signals a match. A match will set the Output ...
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... CTC mode does not have the double buffering feature. If the new value written to OCR1A is lower than the current value of TCNT1, the counter will miss the Compare Match. The counter will then have to count to ATtiny40 88 summarises the different modes of operation. ...
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Compare Match can occur. As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX ...
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... OCR1B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit ATtiny40 90 MAX - 1 MAX shows the setting of OCF1A and OCF1B in Normal mode ...
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The same temporary register is shared between all 16-bit registers. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in ...
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... SREG,r18 ret C Code Example unsigned int TIM1_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1H/L value in the r17:r16 register pair. ATtiny40 92 unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1L ...
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The following code examples show how atomic write of the TCNT1H/L register con- tents. Writing any of the OCR1A/B registers can be done by using the same principle. Assembly Code Example TIM1_WriteTCNT1: C Code Example void TIM1_WriteTCNT1( ...
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... Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ation” on page • Bits 2:0 – CS1[2:0]: Clock Select1, Bits 2, 1, and 0 The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer1. Table 12-4. CS12 ATtiny40 TCW1 ICEN1 ICNC1 ICES1 ...
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Table 12-4. CS12 external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of ...
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... When the TOIE1 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter 1 Inter- rupt Flag Register – TIFR1. ATtiny40 ...
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TIFR – Timer/Counter1 Interrupt Flag Register Bit 0x25 Read/Write Initial Value • Bit 7 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) ...
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... Figure 13-1. T0 Pin Sampling Tn clk I/O The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. ATtiny40 98 ). Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O pulse for each positive (CSn[2: negative ...
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Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...
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... When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. • Bit 4 – PSR: Prescaler Reset Timer/Counter When this bit is one, the Timer/Counter prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. ATtiny40 100 ...
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Analog Comparator The analog comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
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... Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed, internal bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. ATtiny40 102 Analog Comparator Multiplexed Input MUX[3:0] ...
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Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay clock cycles. • Bit 4 – ACI: Analog Comparator ...
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... PIN Register bit will always read as zero when this bit is set. When used as an analog input but not required as a digital input the power consumption in the digital input buffer can be reduced by writing this bit to logic one. ATtiny40 104 14-3. Selecting Level of Analog Comparator Hysteresis ...
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... Sleep Mode Noise Canceler 15.2 Overview ATtiny40 features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). The ADC is wired to a 13-channel analog multiplexer, which allows the ADC to measure the voltage at 12 single-ended input pins, or from one internal, single-ended voltage channel coming from the internal temperature sensor. Voltage inputs are referred to 0V (GND). ...
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... The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared recommended to switch off the ADC before entering power saving sleep modes. ATtiny40 106 8-BIT DATA BUS ADMUX ...
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The ADC converts an analog input voltage to a 10-bit digital value using successive approxima- tion. The minimum value represents GND and the maximum value represents the reference voltage. The ADC voltage reference is selected by writing the REFS bit ...
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... ADC can be higher than 200 kHz to get a higher sample rate not recommended to use a higher input clock frequency than 1 MHz. Figure 15-3. ADC Prescaler The ADC module contains a prescaler, as illustrated in ates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The ATtiny40 108 ADTS[2:0] ADIF SOURCE 1 ...
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ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is ...
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... ADC Clock Trigger Source ADATE ADIF ADCH ADCL In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. See Figure 15-7. ADC Timing Diagram, Free Running Conversion ATtiny40 110 Sample & Prescaler ...
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For a summary of conversion times, see Table 15-1. Condition First conversion Normal conversions Auto Triggered conversions Free Running conversion 15.6 Changing Channel or Reference Selection The MUX and REFS bits in the ADMUX Register are single buffered through a ...
Page 112
... S/H capacitor, which can vary widely. With slowly varying signals the user is recommended to use sources with low impedance, only, since this minimizes the required charge transfer to the S/H capacitor. ATtiny40 112 ) indicates the conversion range for the ADC. Single ended REF will result in codes close to 0x3FF ...
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In order to avoid distortion from unpredictable signal convolution, signal components higher than the Nyquist frequency (f quency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 15-8. Analog Input Circuitry Note: 15.9 Noise ...
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... Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 15-10. Gain Error Output Code ATtiny40 114 Offset Error Ideal ADC Actual ADC ...
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Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 15-11. Integral Non-linearity (INL) Output Code ...
Page 116
... ADCH and ADCL are the ADC data registers the fixed slope coefficient and T the temperature sensor offset. Typically very close to 1.0 and in single-point calibration the coefficient may be omitted. Where higher accuracy is required the slope coefficient should be evaluated based on measurements at two temperatures. ATtiny40 116 ADC is the voltage on the selected input pin and V ...
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Register Description 15.13.1 ADMUX – ADC Multiplexer Selection Register Bit 0x10 Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bit 6 – REFS: Reference Selection Bit ...
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... If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC[9:0]: ADC Conversion Result These bits represent the result from the conversion, as detailed in page 116. ATtiny40 118 Single-Ended Input channel Selections (Continued) (1) 1. See “Temperature Measurement” on page ...
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ADCSRA – ADC Control and Status Register A Bit 0x12 Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning ...
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... If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set Table 15-6. ADTS2 ATtiny40 120 ADC Prescaler Selections (Continued) ADPS1 1 ...
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Table 15-6. ADTS2 15.13.5 DIDR0 – Digital Input Disable Register 0 Bit 0x0D Read/Write Initial Value • Bits 7:0 – ADC7D:ADC0D: ADC[7:0] Digital Input Disable When a bit is written logic one, the digital input buffer on the corresponding ADC ...
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... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 16.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATtiny40 and peripheral devices or between several AVR devices. The SPI module is illustrated in Figure Figure 16-1. SPI Block Diagram Note: ATtiny40 122 16-1 ...
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To enable the SPI module, the PRSPI bit in the Power Reduction Register must be written to zero. See The interconnection between Master and Slave CPUs with SPI is shown in 123. The system consists of two shift Registers, and ...
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... SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for transmission complete in sbrsr16, SPIF rjmp Wait_Transmit ret ATtiny40 124 Table 16-1 on page 124. For more details on automatic port overrides, refer to 52. SPI Pin Overrides Direction, Master SPI User Defined Input User Defined ...
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C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: 8263A–AVR–08/10 (1) ...
Page 126
... SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: ATtiny40 126 (1) ; ...
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The MSTR bit in SPCR is cleared and the SPI system becomes a Slave result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. 2. The SPIF Flag in SPSR is set, and ...
Page 128
... When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. ATtiny40 128 MSB Bit 6 LSB ...
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When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written ...
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... Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. ATtiny40 130 7 6 ...
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... One bus can have several masters, and an arbitration process handles priority if two or more masters try to transmit at the same time. The TWI module in ATtiny40 implements slave functionality, only. Lost arbitration, errors, colli- sions and clock holds on the bus are detected in hardware and indicated in separate status flags ...
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... After all data packets (DATA) are transferred, the mas- ter issues a STOP condition (P) on the bus to end the transaction. The receiver must acknowledge (A) or not-acknowledge (A) each byte received. Figure 17-2 Figure 17-2. Basic TWI Transaction Diagram Topology SDA SCL ATtiny40 132 illustrates the TWI bus topology. TWI ...
Page 133
The master provides the clock signal for the transaction, but a device connected to the bus is allowed to stretch the low level period of the clock to decrease the clock speed. 17.3.1 Electrical Characteristics The TWI follows the electrical ...
Page 134
... START condition followed by an address packet with direction bit set to one (ADRESS+R). The addressed slave must acknowledge the address for the master to be allowed to continue the transaction. ATtiny40 134 illustrates the Master Write transaction. The master initiates the transaction by issu- ...
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Figure 17-6. Master Read Transaction S Given that the slave acknowledges the address, the master can start receiving data from the slave. There are no limitations to the number of data packets that can be transferred. The slave transmits the ...
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... SCL line at the same time. The algorithm is based on the same principles used for clock stretching previously described. two masters are competing for the control over the bus clock. The SCL line is the wired-AND result of the two masters clock outputs. ATtiny40 136 DEVICE1_SDA DEVICE2_SDA ...
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Figure 17-10. Clock Synchronization DEVICE1_SCL DEVICE2_SCL SCL (wired-AND) A high to low transition on the SCL line will force the line low for all masters on the bus and they start timing their low clock period. The timing length of ...
Page 138
... Case 2: Address packet accepted - Direction bit cleared If the R/W Direction flag is cleared this indicates a master write operation. The SCL line is forced low, stretching the bus clock. If ACK is sent by the slave, the slave will wait for data to be ATtiny40 138 SLAVE ADDRESS INTERRUPT ...
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Data, Repeated START or STOP can be received after this. If NACK is indicated the slave will wait for a new START condition and address match. 17.4.1.3 Case 3: Collision If the slave is not able to send a ...
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... Bits 1:0 – TWCMD[1:0]: TWI Command Writing these bits triggers the slave operation as defined by depends on the TWI slave interrupt flags, TWDIF and TWASIF. The Acknowledge Action is only executed when the slave receives data bytes or address byte from the master. ATtiny40 140 7 6 ...
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Table 17-2. TWCMD[1:0] Writing the TWCMD bits will automatically release the SCL line and clear the TWCH and slave interrupt flags. TWAA and TWCMDn bits can be written at the same time. Acknowledge Action will then be exe- cuted before ...
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... When using 10-bit addressing the address match logic only support hardware address recogni- tion of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 of the slave address. The next byte received is then bits the 10-bit address, but this must be handled by software. ATtiny40 142 7 6 ...
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When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on ...
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... Touch Sensing ATtiny40 is optimized for QTouch QTouch Atmel AVR ATtiny40 144 ® Library. ® Library is a royalty free software library for developing touch applications on standard ® Microcontrollers. 8263A–AVR–08/10 ...
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Programming Interface 19.1 Features • Physical Layer: – Synchronous Data Transfer – Bi-directional, Half-duplex Receiver And Transmitter – Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits – Parity Error Detection, ...
Page 146
... The TPI physical layer supports a fixed frame format. A frame consists of one character, eight bits in length, and one start bit, a parity bit and two stop bits. Data is transferred with the least significant bit first. ATtiny40 146 Tiny Programming Interface enable input Tiny Programming Interface clock input ...
Page 147
Figure 19-3. Serial frame format. TPICLK TPIDATA Symbols used in ST: D0-D7: Data bits (least significant bit sent first) P: SP1: SP2: 19.3.4 Parity Bit Calculation The parity bit is always calculated using even parity. The value of the bit ...
Page 148
... A possible drive contention may occur, if the external programmer and the TPI physical layer drive the TPIDATA line simultaneously. In order to reduce the effect of the drive contention, a collision detection mechanism is supported. The collision detection is based on the way the TPI physical layer drives the TPIDATA line. ATtiny40 148 TPICLK TPIDATA ...
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The TPIDATA line is driven by a tri-state, push-pull driver with internal pull-up. The output driver is always enabled when a logical zero is sent. When sending successive logical ones, the output is only driven actively during the first clock ...
Page 150
... The instructions allow the external programmer to access the TPI, the NVM Controller and the NVM memories. All instructions except SKEY require one byte oper- and following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions are byte-sized. ATtiny40 150 page 150. ...
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The TPI instruction set is summarised in Table 19-1. Mnemonic SLD SLD SST SST SSTPR SIN SOUT SLDCS SSTCS SKEY 19.5.1 SLD - Serial LoaD from data space using indirect addressing The SLD instruction uses indirect addressing to load data ...
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... The SSTCS instruction stores the data byte that is shifted into the TPI physical layer shift regis- ter to the TPI Control and Status Space. The SSTCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction, as shown in Table 19-8. Operation CSS[a] ATtiny40 152 Table 19-4. The Serial Store to Pointer Register (SSTPR) Instruction Opcode ...
Page 153
SKEY - Serial KEY signaling The SKEY instruction is used to signal the activation key that enables NVM programming. The SKEY instruction is followed by the 8 data bytes that includes the activation key, as shown in Table 19-9. ...
Page 154
... Additional delays are not inserted when changing from transmission mode to reception. The total idle time when changing from reception to transmission mode is Guard Time plus two IDLE bits. Table 19-13. Guard Time Settings GT2 ATtiny40 154 Name Bit 7 Bit 6 Bit 5 TPIPCR – ...
Page 155
Table 19-13. Guard Time Settings GT2 The default Guard Time is 128 IDLE bits. To speed up the communication, the Guard Time should be set to the shortest safe value. 19.7.3 TPISR – Tiny Programming Interface Status Register Bit CSS: ...
Page 156
... The external programmer can read and program the NVM via the Tiny Programming Interface (TPI). In the external programming mode all NVM can be read and programmed, except the signature and the calibration sections which are read-only. NVM can be programmed at 5V, only. ATtiny40 156 8263A–AVR–08/10 ...
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... The ATtiny40 has the following, embedded NVM: • Non-Volatile Memory Lock Bits • Flash memory with four separate sections 20.3.1 Non-Volatile Memory Lock Bits The ATtiny40 provides two Lock Bits, as shown in Table 20-1. Lock Bit NVLB2 NVLB1 The Lock Bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the addi- tional security shown in command, only ...
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... Flash Memory The embedded Flash memory of ATtiny40 has four separate sections, as shown in Table 20-3. Section Code (program memory) Configuration Signature Calibration Notes: 20.3.3 Configuration Section ATtiny40 has one configuration byte, which resides in the configuration section. See Table 20-4. Configuration word address 0x00 0x01 ... 0x1F Table 20-5 into the configuration byte ...
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... Most of this memory section is reserved for internal use, as shown in Table 20-6. Signature word address 0x00 0x01 0x02 ... 0x3F ATtiny40 has a three-byte signature code, which can be used to identify the device. The three bytes reside in the signature section, as shown in given in Table 20-7. Part ATtiny40 20.3.5 Calibration Section ATtiny40 has one calibration byte ...
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... Programming any part of the NVM will automatically inhibit the following operations: • All programming to any other part of the NVM • All reading from any NVM location The ATtiny40 supports only external programming. Internal programming operations to the NVM have been disabled, which means any internal attempt to write or erase NVM locations will fail. 20.4.1 ...
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The most significant bits of the data space address select the NVM Lock bits or the Flash sec- tion mapped to the data memory. The word address within a page (WADDR) is held by the bits [WADDRMSB:1], and the page ...
Page 162
... Send IDLE character as described in section 5. Write a dummy byte to the low byte of the next configuration word location 6. Write a dummy byte to the high byte of the same configuration word location. 7. Send IDLE character as described in section ATtiny40 162 “Supported Characters” on page 147 “Supported Characters” on page 147 “ ...
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... NVM Lock Word location. 4. Wait until the NVMBSY bit has been cleared. 20.5 Self programming The ATtiny40 doesn't support internal programming. 20.6 External Programming The method for programming the Non-Volatile Memories by means of an external programmer is referred to as external programming. External programming can be done both in-system or in mass production ...
Page 164
... This bit is set when a program operation is started, and it remains set until the operation has been completed. • Bits 6:0 – Res: Reserved Bits These bits are reserved and will always read as zero. ATtiny40 164 “TPISR – Tiny Programming Interface Status Register” on page 7 ...
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Electrical Characteristics 21.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...
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... Values are with external clock using methods described in is enabled (PRR = 0xFF) and there is no I/O drive. 8. BOD Disabled. 21.3 Speed The maximum operating frequency of the device depends on V relationship between maximum frequency vs. V Figure 21-1. Maximum Frequency vs. V ATtiny40 166 = -40°C to +85°C (Continued) A Condition Min Active 1MHz ...
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Clock Characteristics 21.4.1 Accuracy of Calibrated Internal Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics ...
Page 168
... RST t TOUT 21.5.1 Power-On Reset Table 21-5. Symbol V POR V POA SR ON Note: 21.5.2 Brown-Out Detection Table 21-6. BODLEVEL[2:0] Fuses Note: ATtiny40 168 Reset and Internal Voltage Characteristics Parameter Condition RESET Pin Threshold Voltage V CC Internal bandgap voltage Minimum pulse width RESET Pin V ...
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Analog Comparator Characteristics Table 21-7. Analog Comparator Characteristics, T Symbol Parameter V Input Offset Voltage AIO I Input Leakage Current LAC Analog Propagation Delay (from saturation to slight overdrive) t APD Analog Propagation Delay (large step change) t Digital ...
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... TPID ATA TPIC LK Table 21-9. Symbol 1/t CLCL t CLCL t CLCH t CHCH t IVCH t CHIX t CLOV ATtiny40 170 t t IVCH CHIX t t CLC H CHCL t CLCL Serial Programming Characteristics, T Parameter Clock Frequency Clock Period Clock Low Pulse Width Clock High Pulse Width Data Input to Clock High Setup Time ...
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Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...
Page 172
... Figure 22-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 ATtiny40 172 below can be used for calculating typical current consumption for other supply volt- Additional Current Consumption (percentage) in Active and Idle mode Current consumption additional to active mode with external clock (see Table 22-1 and Table 2 % ...
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Figure 22-2. Active Supply Current vs. Frequency ( MHz) Figure 22-3. Active Supply Current vs. V 4,5 3,5 2,5 1,5 0,5 8263A–AVR–08/ 1 ...
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... Figure 22-4. Active Supply Current vs 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 Figure 22-5. Active Supply Current vs. V 0,12 0,1 0,08 0,06 0,04 0,02 0 ATtiny40 174 1,5 2 2,5 3 1,5 2 2,5 3 (Internal Oscillator, 1 MHz) CC 3,5 4 4,5 V [V] CC (Internal Oscillator, 128 kHz) CC 3,5 4 4 °C 25 °C -40 °C 5 5,5 -40 °C 25 °C 85 °C 5 5,5 8263A–AVR–08/10 ...
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Figure 22-6. Active Supply Current vs. V 0,045 0,04 0,035 0,03 0,025 0,02 0,015 0,01 0,005 22.3 Current Consumption in Idle Mode Figure 22-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0,12 0,1 0,08 0,06 0,04 0,02 ...
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... Figure 22-8. Idle Supply Current vs. Frequency ( MHz) 1,4 1,2 1 0,8 0,6 0,4 0,2 0 Figure 22-9. Idle Supply Current vs 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 ATtiny40 176 1 1,5 2 2,5 3 3 Frequency [MHz] (Internal Oscillator, 8 MHz) 3,5 4 4,5 V [V] CC 5.5 V 5.0 V 4 °C 25 °C -40 °C 5 5,5 8263A–AVR–08/10 ...
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Figure 22-10. Idle Supply Current vs. V 0,3 0,25 0,2 0,15 0,1 0,05 Figure 22-11. Idle Supply Current vs. V 0,03 0,025 0,02 0,015 0,01 0,005 8263A–AVR–08/ 1 1,5 2 2,5 3 (Internal ...
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... Figure 22-12. Idle Supply Current vs. V 0,025 0,02 0,015 0,01 0,005 0 22.4 Current Consumption in Power-down Mode Figure 22-13. Power-down Supply Current vs. V 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 ATtiny40 178 CC 1,5 2 2,5 3 1,5 2 2,5 3 (Internal Oscillator, 32kHz) 3,5 4 4,5 V [V] CC (Watchdog Timer Disabled) CC 3,5 4 4,5 V [V] CC -40 °C 25 °C 85 °C 5 5,5 85 °C 25 °C -40 °C 5 5,5 8263A–AVR–08/10 ...
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Figure 22-14. Power-down Supply Current vs 22.5 Current Consumption in Reset Figure 22-15. Reset Supply Current vs. V 4,5 3,5 2,5 1,5 0,5 8263A–AVR–08/ 1 Clock 4 3 ...
Page 180
... Current Consumption of Peripheral Units Figure 22-16. ADC Current vs. V 400 350 300 250 200 150 100 50 0 Figure 22-17. Analog Comparator Current vs. V 140 120 100 ATtiny40 180 CC 1,5 2 2,5 3 1,5 2 2,5 3 3 [V] CC (Frequency 1 MHz) CC 3 [V] CC 5,5 5,5 8263A–AVR–08/10 ...
Page 181
Figure 22-18. Watchdog Timer Current vs Figure 22-19. Brownout Detector Current vs 8263A–AVR–08/ 1 1 3,5 4 ...
Page 182
... Pull-up Resistors Figure 22-20. I/O pin Pull-up Resistor Current vs. Input Voltage ( Figure 22-21. I/O Pin Pull-up Resistor Current vs. input Voltage ( ATtiny40 182 0 0,2 0,4 0,6 0 1.8V 1,2 1,4 1,6 1 2.7V [ °C 85 °C -40 ° ...
Page 183
Figure 22-22. I/O pin Pull-up Resistor Current vs. Input Voltage (V 160 140 120 100 Figure 22-23. Reset Pull-up Resistor Current vs. Reset Pin Voltage ( 8263A–AVR–08/ ...
Page 184
... Figure 22-24. Reset Pull-up Resistor Current vs. Reset Pin Voltage ( Figure 22-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 120 100 ATtiny40 184 2.7V [V] RESET = 5V [V] RESET 25 °C -40 °C 85 ° ° ...
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Output Driver Strength Figure 22-26. V 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 Figure 22-27. V 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 8263A–AVR–08/10 : Output Voltage vs. Sink Current (I/O Pin ...
Page 186
... Figure 22-28 0,8 0,6 0,4 0,2 0 Figure 22-29 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 0 ATtiny40 186 : Output Voltage vs. Sink Current (I/O Pin Output Voltage vs. Source Current (I/O Pin 0 [mA 1.8V) CC 2,5 3 3,5 4 4,5 I [mA °C 25 °C -40 °C 20 -40 °C 25 °C 85 °C 5 8263A–AVR–08/10 ...
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Figure 22-30. V 3,5 2,5 1,5 0,5 Figure 22-31. V 5,1 4,9 4,8 4,7 4,6 4,5 4,4 4,3 4,2 4,1 8263A–AVR–08/10 : Output Voltage vs. Source Current (I/O Pin ...
Page 188
... Figure 22-32 0,8 0,6 0,4 0,2 0 Figure 22-33 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 0 ATtiny40 188 : Output Voltage vs. Sink Current (Reset Pin as I/ Output Voltage vs. Sink Current (Reset Pin as I/ 1.8V [mA 3V [mA °C 25 °C -40 ° ° ...
Page 189
Figure 22-34. V 1,8 1,6 1,4 1,2 0,8 0,6 0,4 0,2 Figure 22-35. V 1,6 1,4 1,2 0,8 0,6 0,4 0,2 8263A–AVR–08/10 : Output Voltage vs. Sink Current (Reset Pin as I/ 0,5 1 ...
Page 190
... Figure 22-36 2,5 2 1,5 1 0,5 0 Figure 22-37. V 4,5 4 3,5 3 2,5 2 1,5 1 0,5 0 ATtiny40 190 : Output Voltage vs. Source Current (Reset Pin as I/ 0,1 0,2 0,3 0,4 : Output Voltage vs. Source Current (Reset Pin as I/ 0,1 0,2 0,3 0 0,5 0,6 0,7 0,8 0,9 I [mA 0,5 0,6 0,7 0,8 0,9 I [mA °C 25 °C -40 ° °C 25 °C -40 °C 1 8263A–AVR–08/10 ...
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Input Thresholds and Hysteresis Figure 22-38. V 2,5 1,5 0,5 Figure 22-39. V 2,5 1,5 0,5 8263A–AVR–08/10 : Input Threshold Voltage vs 1 Input Threshold Voltage vs ...
Page 192
... Figure 22-40. V 0,6 0,5 0,4 0,3 0,2 0,1 0 1,5 Figure 22-41. V 3,5 3 2,5 2 1,5 1 0,5 0 1,5 ATtiny40 192 -V : Input Hysteresis vs -40 °C 25 °C 85 ° Input Threshold Voltage vs 2,5 3 (I/O Pin) CC 3 [V] CC (Reset Pin as I/O, Read as ‘1’) CC 3 [V] CC 5,5 -40 °C 25 °C 85 °C 5,5 8263A–AVR–08/10 ...
Page 193
Figure 22-42. V 2,5 1,5 0,5 Figure 22-43. V 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 8263A–AVR–08/10 : Input Threshold Voltage vs 1 Input Hysteresis vs ...
Page 194
... BOD, Bandgap and Reset Figure 22-44. BOD Threshold vs Temperature (BODLEVEL is 4.3V) 4,34 4,32 4,3 4,28 4,26 4,24 4,22 4,2 4,18 4,16 -40 Figure 22-45. BOD Threshold vs Temperature (BODLEVEL is 2.7V) 2,76 2,74 2,72 2,7 2,68 2,66 2,64 2,62 -40 ATtiny40 194 - Temperature [°C] - Temperature [° 100 100 8263A–AVR–08/10 V RISING CC V FALLING CC V RISING CC V FALLING CC ...
Page 195
Figure 22-46. BOD Threshold vs Temperature (BODLEVEL is 1.8V) 1,83 1,82 1,81 1,8 1,79 1,78 1,77 1,76 1,75 -40 Figure 22-47. Bandgap Voltage vs. Supply Voltage 1,09 1,085 1,08 1,075 1,07 1,065 1,06 1,055 1,05 1,045 8263A–AVR–08/10 - ...
Page 196
... Figure 22-48. V 2,5 2 1,5 1 0,5 0 1,5 Figure 22-49. V 2,5 2 1,5 1 0,5 0 ATtiny40 196 : Input Threshold Voltage vs 2 Input Threshold Voltage vs 1,5 2 2,5 3 (Reset Pin, Read as ‘1’) CC 3 [V] CC (Reset Pin, Read as ‘0’) CC 3 [V] CC -40 °C 25 °C 85 °C 5,5 -40 °C 25 °C 85 °C 5,5 8263A–AVR–08/10 ...
Page 197
Figure 22-50. V 0,6 0,5 0,4 0,3 0,2 0,1 Figure 22-51. Minimum Reset Pulse Width vs. V 2500 2000 1500 1000 500 8263A–AVR–08/ Input Hysteresis vs -40 °C 25 °C 85 °C 0 1,5 2 ...
Page 198
... Analog Comparator Offset Figure 22-52. Analog Comparator Offset vs -0,002 -0,004 -0,006 -0,008 -0,01 -0,012 -0,014 22.12 Internal Oscillator Speed Figure 22-53. Watchdog Oscillator Frequency vs. V 0,109 0,108 0,107 0,106 0,105 0,104 0,103 0,102 0,101 0,1 0,099 ATtiny40 198 0 0,5 1 1,5 2 1 2,5 3 3,5 4 4,5 V [V] in ...
Page 199
Figure 22-54. Watchdog Oscillator Frequency vs. Temperature 0,109 0,108 0,107 0,106 0,105 0,104 0,103 0,102 0,101 0,1 0,099 Figure 22-55. Calibrated Oscillator Frequency vs. V 8,5 8,4 8,3 8,2 8,1 8 7,9 7,8 7,7 8263A–AVR–08/10 -40 -20 0 1,5 2 ...
Page 200
... Figure 22-56. Calibrated Oscillator Frequency vs. Temperature 8,3 8,2 8,1 8 7,9 7,8 7,7 Figure 22-57. Calibrated Oscillator Frequency vs, OSCCAL Value ATtiny40 200 -40 - 112 Temperature [°C ] 128 144 160 176 192 208 224 OSCCAL [X1] 5.0 V 3.0 V 1.8 V 100 -40 °C 25 °C 85 °C 240 ...