ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 128

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.5
16.5.1
128
Register Description
ATtiny40
SPCR – SPI Control Register
Figure 16-4. SPI Transfer Format with CPHA = 1
Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient
time for data signals to stabilize. This is shown in
on page 129
Table 16-2.
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
Bit
0x30
Read/Write
Initial Value
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SPI Mode
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
0
1
2
3
and
SPI Modes
SPIE
R/W
7
0
Table 16-4 on page
Conditions
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
SPE
R/W
6
0
MSB
LSB
DORD
R/W
5
0
Bit 6
Bit 1
129.
MSTR
R/W
4
0
Bit 5
Bit 2
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Table
CPOL
R/W
3
0
Bit 4
Bit 3
16-2, which is a summary of
CPHA
R/W
Bit 3
Bit 4
2
0
SPR1
R/W
Bit 2
Bit 5
1
0
Trailing eDge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
SPR0
R/W
Bit 1
Bit 6
0
0
8263A–AVR–08/10
Table 16-3
LSB
MSB
SPCR