ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 41

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.2
9.2.1
8263A–AVR–08/10
External Interrupts
Low Level Interrupt
External Interrupts are triggered by the INT0 pin or any of the PCINT[17:0] pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 or PCINT[17:0] pins are configured as out-
puts. This feature provides a way of generating a software interrupt.
Pin change 0 interrupts PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1
interrupts PCI1 will trigger if any enabled PCINT[11:8] pin toggles. Pin change 2 interrupts PCI1
will trigger if any enabled PCINT[17:12] pin toggles. The PCMSK0, PCMSK1 and PCMSK2 Reg-
isters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT[17:0] are detected asynchronously, which means that these interrupts can be used for
waking the part also from sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as
shown in
and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note
that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock,
as described in
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source
can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in
all sleep modes except Idle).
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
...
“MCUCR – MCU Control Register” on page
RESET: ldi
“Clock System” on page
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
out
ldi
out
sei
<instr>
...
PCINT1
PCINT2
WDT
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_COMPA
TIM0_COMPB
TIM0_OVF
ANA_COMP
ADC
TWI_SLAVE
SPI
QTRIP
r16, high(RAMEND); Main program start
SPH,r16
r16, low(RAMEND) ; to top of RAM
SPL,r16
20.
; PCINT1 Handler
; PCINT2 Handler
; Watchdog Interrupt Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; Timer0 Overflow Handler
; Analog Comparator Handler
; ADC Conversion Handler
; Two-Wire Interface Handler
; Serial Peripheral Interface Handler
; Touch Sensing Handler
; Set Stack Pointer
; Enable interrupts
43. When the INT0 interrupt is enabled
41