ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 39

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ATtiny40

Manufacturer Part Number
ATtiny40
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny40

Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
Yes
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATtiny40-MMHR
Quantity:
6 000
8.5.2
8263A–AVR–08/10
RSTFLR – Reset Flag Register
Table 8-3.
The Reset Flag Register provides information on which reset source caused an MCU Reset.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-Out Reset Flag
This bit is set if a Brown-Out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-On Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the RSTFLR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
Bit
0x3B
Read/Write
Initial Value
WDP3
1
1
1
1
1
1
WDP2
0
0
1
1
1
1
Watchdog Timer Prescale Select (Continued)
R
7
0
WDP1
1
1
0
0
1
1
R
6
0
WDP0
0
1
0
1
0
1
R
5
0
R
4
0
WDT Oscillator Cycles
WDRF
Number of
R/W
X
3
BORF
R/W
X
2
Reserved
EXTRF
R/W
X
1
PORF
R/W
Typical Time-out
X
0
at V
CC
RSTFLR
= 5.0V
39

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