ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 138

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Figure 17-11. TWI Slave Operation
17.4.1
17.4.1.1
17.4.1.2
138
S1
S2
SW
Sn
Driver software
The master provides data
on the bus
Slave provides data on
the bus
Diagram connections
ATtiny40
Receiving Address Packets
S3
S
Case 1: Address packet accepted - Direction bit set
Case 2: Address packet accepted - Direction bit cleared
ADDRESS
The number of interrupts generated is kept at a minimum by automatic handling of most condi-
tions. Quick Command can be enabled to auto trigger operations and reduce software
complexity.
Promiscuous Mode can be enabled to allow the slave to respond to all received addresses.
When the TWI slave is properly configured, it will wait for a START condition to be detected.
When this happens, the successive address byte will be received and checked by the address
match logic, and the slave will ACK the correct address. If the received address is not a match,
the slave will not acknowledge the address and wait for a new START condition.
The slave Address/Stop Interrupt Flag is set when a START condition succeeded by a valid
address packet is detected. A general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition, is an illegal operation and the
Bus Error flag is set.
The R/W Direction flag reflects the direction bit received with the address. This can be read by
software to determine the type of operation currently in progress.
Depending on the R/W direction bit and bus condition one of four distinct cases (1 to 4) arises
following the address packet. The different cases must be handled in software.
If the R/W Direction flag is set, this indicates a master read operation. The SCL line is forced
low, stretching the bus clock. If ACK is sent by the slave, the slave hardware will set the Data
Interrupt Flag indicating data is needed for transmit. If NACK is sent by the slave, the slave will
wait for a new START condition and address match.
If the R/W Direction flag is cleared this indicates a master write operation. The SCL line is forced
low, stretching the bus clock. If ACK is sent by the slave, the slave will wait for data to be
Condition Enabled
Interrupt on STOP
SLAVE ADDRESS INTERRUPT
Collision
(SMBus)
W
R
SW
SW
SW
SW
Release
Hold
A
A
A
A
S1
S1
S1
Sr
P
S2
S3
DATA
SLAVE DATA INTERRUPT
SW
SW
A/A
Sr
P
DATA
S2
S3
8263A–AVR–08/10
A
A
S1