ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 19

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.4
5.4.1
5.4.2
8263A–AVR–08/10
Register Description
RAMAR – RAM Address Register
RAMDR – RAM Data Register
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such status flags. The CBI and SBI instructions work on registers in the address range 0x00
to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
• Bits 7:0 – RAMAR[7:0]: RAM Address
The RAMAR register contains the RAM address bits. The RAM data bytes are addressed lin-
early in the range 0..255. The initial value of RAMAR is undefined and a proper value must be
therefore written before the RAM may be accessed.
• Bits 7:0 – RAMDR[7:0]: RAM Data
For the RAM write operation, the RAMDR register contains the RAM data to be written to the
RAM in address given by the RAMAR register. For the RAM read operation, the RAMDR con-
tains the data read out from the RAM at the address given by RAMAR.
Bit
0x20
Read/Write
Initial Value
Bit
0x1F
Read/Write
Initial Value
RAMAR7
RAMDR7
R/W
R/W
X
X
7
7
RAMAR6
RAMDR6
R/W
R/W
X
X
6
6
RAMAR5
RAMDR5
R/W
R/W
X
X
5
5
RAMAR4
RAMDR4
R/W
R/W
4
X
4
X
RAMAR3
RAMDR3
R/W
R/W
3
X
3
X
RAMAR2
RAMDR2
R/W
R/W
X
X
2
2
RAMAR1
RAMDR1
R/W
R/W
X
X
1
1
RAMAR0
RAMDR0
R/W
R/W
0
X
0
X
RAMAR
RAMDR
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