ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 142

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.4
142
ATtiny40
TWSA – TWI Slave Address Register
• Bit 5 – TWCH: TWI Clock Hold
This bit is set when the slave is holding the SCL line low.
This bit is read-only, and set when TWDIF or TWASIF is set. The bit can be cleared indirectly by
clearing the interrupt flags and releasing the SCL line.
• Bit 4 – TWRA: TWI Receive Acknowledge
This bit contains the most recently received acknowledge bit from the master.
This bit is read-only. When zero, the most recent acknowledge bit from the maser was ACK and,
when one, the most recent acknowledge bit was NACK.
• Bit 3 – TWC: TWI Collision
This bit is set when the slave was not able to transfer a high data bit or a NACK bit. When a col-
lision is detected, the slave will commence its normal operation, and disable data and
acknowledge output. No low values are shifted out onto the SDA line.
This bit is cleared by writing a one to it. The bit is also cleared automatically when a START or
Repeated START condition is detected.
• Bit 2 – TWBE: TWI Bus Error
This bit is set when an illegal bus condition has occured during a transfer. An illegal bus condi-
tion occurs if a Repeated START or STOP condition is detected, and the number of bits from the
previous START condition is not a multiple of nine.
This bit is cleared by writing a one to it.
• Bit 1 – TWDIR: TWI Read/Write Direction
This bit indicates the direction bit from the last address packet received from a master. When
this bit is one, a master read operation is in progress. When the bit is zero a master write opera-
tion is in progress.
• Bit 0 – TWAS: TWI Address or Stop
This bit indicates why the TWASIF bit was last set. If zero, a stop condition caused TWASIF to
be set. If one, address detection caused TWASIF to be set.
The slave address register contains the TWI slave address used by the slave address match
logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address rec-
ognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave
address. The least significant bit (TWSA0) is used for general call address recognition. Setting
TWSA0 enables general call address recognition logic.
When using 10-bit addressing the address match logic only support hardware address recogni-
tion of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent
bits 9 and 8 of the slave address. The next byte received is then bits 7 to 0 in the 10-bit address,
but this must be handled by software.
Bit
0x2A
Read/Write
Initial Value
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
TWSA[7:0]
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
8263A–AVR–08/10
TWSA