ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 83

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12. Timer/Counter1
12.1
12.2
12.2.1
8263A–AVR–08/10
Features
Overview
Registers
•
•
•
•
•
Timer/Counter1 is a general purpose 8/16-bit Timer/Counter module, with two/one Output Com-
pare units and Input Capture feature.
The general operation of Timer/Counter1 is described in 8/16-bit mode. A simplified block dia-
gram of the 8/16-bit Timer/Counter is shown in
including I/O bits and I/O pins, are shown in bold. For actual placement of I/O pins, refer to
Description” on page
Description” on page
Figure 12-1. 8/16-bit Timer/Counter Block Diagram
The Timer/Counter1 Low Byte Register (TCNT1L) and Output Compare Registers (OCR1A and
OCR1B) are 8-bit registers. Interrupt request (abbreviated Int.Req. in
Clear Timer on Compare Match (Auto Reload)
One Input Capture unit
Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, ICF1)
8-bit Mode with Two Independent Output Compare Units
16-bit Mode with One Independent Output Compare Unit
TCCRnA
TCNTnH
OCRnB
=
Timer/Counter
94.
2. Device-specific I/O Register and bit locations are listed in the
Direction
Count
Clear
TCNTnL
OCRnA
=
Control Logic
TOP
Figure
Detector
Edge
clk
=
Tn
12-1. CPU accessible I/O Registers,
Canceler
Fixed TOP value
( From Prescaler )
Noise
Figure
Clock Select
Detector
Edge
TOVn (Int. Req.)
12-1) signals are all
OCnA (Int. Req.)
OCnB (Int. Req.)
ICFn (Int. Req.)
ICPn
“Register
Tn
“Pin
83