ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 85

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.5
8263A–AVR–08/10
Input Capture Unit
Signal description (internal signals):
The counter is incremented at each timer clock (clk
restarts from BOTTOM. The counting sequence is determined by the setting of the CTC1 bit
located in the Timer/Counter Control Register (TCCR1A). For more details about counting
sequences, see
internal clock source, selected by the Clock Select bits (CS1[2:0]). When no clock source is
selected (CS1[2:0] = 0) the timer is stopped. However, the TCNT1 value can be accessed by the
CPU, regardless of whether clk
counter clear or count operations. The Timer/Counter Overflow Flag (TOV1) is set when the
counter reaches the maximum value and it can be used for generating a CPU interrupt.
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-
tiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-
nal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in
the block diagram that are not directly a part of the Input Capture unit are gray shaded.
Figure 12-2. Input Capture Unit Block Diagram
The Output Compare Register OCR1A is a dual-purpose register that is also used as an 8-bit
Input Capture Register ICR1. In 16-bit Input Capture mode the Output Compare Register
ICP0
count
clk
top
WRITE
Tn
OCR0B (8-bit)
TEMP (8-bit)
“Modes of Operation” on page
ICR0 (16-bit Register)
Increment or decrement TCNT1 by 1.
Timer/Counter clock, referred to as clk
Signalize that TCNT1 has reached maximum value.
OCR0A (8-bit)
T1
is present or not. A CPU write overrides (has priority over) all
DATA BUS
Canceler
Noise
ICNC0
87. clk
T1
(8-bit)
T1
) until it passes its TOP value and then
TCNT0H (8-bit)
can be generated from an external or
T1
TCNT0 (16-bit Counter)
in the following.
Detector
ICES0
Figure
Edge
12-2. The elements of
TCNT0L (8-bit)
ICF0 (Int.Req.)
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