ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 23

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6. System Clock and Clock Options
6.1
6.1.1
6.1.2
6.1.3
8048B–AVR–03/09
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
I/O
Figure 6-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 6-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
Also note that start condition detection in the USI module is carried out asynchronously when
clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
CPU
FLASH
I/O
is halted.
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
General I/O
Modules
External Clock
clk
I/O
System Clock
Control Unit
AVR Clock
Multiplexer
Prescaler
Clock
ADC
31. The clock systems are detailed below.
Source clock
clk
ADC
CPU Core
clk
clk
Reset Logic
CPU
FLASH
Watchdog clock
Watchdog Timer
RAM
Watchdog
Oscillator
Calibrated RC
Flash and
EEPROM
Oscillator
“Power Manage-
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