ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 81

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.5
8048B–AVR–03/09
Output Compare Unit
Figure 12-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the
timer is stopped. However, the TCNTn value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGMn1 and WGMn0 bits located in
the Timer/Counter Control Register (TCCRnA) and the WGMn2 bit located in the Timer/Counter
Control Register B (TCCRnB). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare output OCnA. For more
details about advanced counting sequences and waveform generation, see
tion” on page
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by
the WGMn1:0 bits. TOVn can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNTn with the Output Compare Registers
(OCRnA and OCRnB). Whenever TCNTn equals OCRnA or OCRnB, the comparator signals a
match. A match will set the Output Compare Flag (OCFnA or OCFnB) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGMn2:0 bits and Compare Output mode (COMnx1:0) bits. The max
and bottom signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation. See
Figure 12-3 on page 82
count
direction
clear
clk
top
bottom
Tn
Tn
84.
is present or not. A CPU write overrides (has priority over) all counter clear or
DATA BUS
TCNTn
Tn
shows a block diagram of the Output Compare unit.
). clk
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNTn has reached maximum value.
Signalize that TCNTn has reached minimum value (zero).
Tn
can be generated from an external or internal clock source,
direction
count
clear
bottom
Control Logic
“Modes of Operation” on page
top
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
Tn
in the following.
“Modes of Opera-
84.
Tn
81