ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 96

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.9.12
12.9.13
12.9.14
96
ATtiny43U
TIMSK1 – Timer/Counter 1 Interrupt Mask Register
TIFR0 – Timer/Counter 0 Interrupt Flag Register
TIFR1 – Timer/Counter 1 Interrupt Flag Register
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCIEnB: Timer/Countern Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Countern occurs, i.e., when the OCFnB bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFRn.
• Bit 1 – OCIEnA: Timer/Countern Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Countern Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Countern occurs, i.e., when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register – TIFRn.
• Bit 0 – TOIEn: Timer/Countern Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Coun-
tern Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
Timer/Countern occurs, i.e., when the TOVn bit is set in the Timer/Counter n Interrupt Flag Reg-
ister – TIFRn.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCFnB: Output Compare Flag n B
The OCFnB bit is set when a Compare Match occurs between the Timer/Countern and the data
in OCRnB – Output Compare Registern B. OCFnB is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt Enable),
and OCFnB are set, the Timer/Countern Compare Match Interrupt is executed.
Bit
0x0C (0x2C)
Read/Write
Initial Value
Bit
0x38 (0x58)
Read/Write
Initial Value
Bit
0x0B (0x2B)
Read/Write
Initial Value
R
7
–
0
R
R
7
–
0
7
–
0
R
6
–
0
R
R
6
–
0
6
–
0
R
5
–
0
5
–
R
0
5
–
R
0
R
4
–
0
R
R
4
–
0
4
–
0
R
3
–
0
R
R
3
–
0
3
–
0
OCIE1B
OCF0B
OCF1B
R/W
R/W
R/W
2
0
2
0
2
0
OCIE1A
OCF0A
OCF1A
R/W
R/W
R/W
1
0
1
0
1
0
TOIE1
TOV0
TOV1
R/W
R/W
R/W
0
0
0
0
0
0
8048B–AVR–03/09
TIMSK1
TIFR0
TIFR1