ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 88

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.8
88
Timer/Counter Timing Diagrams
ATtiny43U
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COMnx1:0 to three: Setting the COMnA0 bits to
one allows the OCnA pin to toggle on Compare Matches if the WGMn2 bit is set. This option is
not available for the OCnB pin (See
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OCnx Register at the Compare Match between OCRnx
and TCNTn when the counter increments, and setting (or clearing) the OCnx Register at Com-
pare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCRnA Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnA is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guaratee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
The figure shows the count sequence close to the MAX value in all modes other than phase cor-
rect PWM mode.
• OCRnA changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCRnA, and for that reason
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of
an up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
Figure 12-8 on page 89
Figure 12-7 on page 87
f
Table 12-4 on page
OCnxPCPWM
contains timing data for basic Timer/Counter operation.
Figure 12-7 on page
=
----------------- -
N 510
f
clk_I/O
⋅
91). The actual OCnx value will only be
OCn has a transition from high to low
87. When the OCRnA value
Tn
) is therefore shown as a
8048B–AVR–03/09