ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 60
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ATtiny43U
Manufacturer Part Number
ATtiny43U
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny43U
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
0.7 to 5.5
Operating Voltage (vcc)
0.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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10.3.2
10.3.3
60
ATtiny43U
GIMSK – General Interrupt Mask Register
GIFR – General Interrupt Flag Register
If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Table 10-2.
• Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
• Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-
rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
• Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit
0x3B (0x5B)
Read/Write
Initial Value
Bit
0x3A (0x5A)
Read/Write
Initial Value
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00
R
R
7
–
0
7
–
0
0
1
0
1
INTF0
INT0
R/W
R/W
Description
The low level of INT0 generates an interrupt request asynchronously
Any logical change on INT0 generates an interrupt request asynchronously
The falling edge of INT0 generates an interrupt request asynchronously
The rising edge of INT0 generates an interrupt request asynchronously
6
0
6
0
PCIE1
PCIF1
R/W
R/W
5
0
5
0
PCIE0
PCIF0
R/W
R/W
4
0
4
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
R
R
1
–
0
1
–
0
0
–
R
0
0
–
R
0
8048B–AVR–03/09
GIMSK
GIFR
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