ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 58

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

10.2
10.2.1
58
External Interrupts
ATtiny43U
Pin Change Interrupt Timing
The External Interrupts are triggered by the INT0 pin or any of the PCINT pins. Observe that, if
enabled, the interrupts will trigger even if INT0 or the PCINT pins are configured as outputs. This
feature provides a way of generating a software interrupt, as follows.
The PCMSK0 and PCMSK1 Registers control which pins contribute to the pin change interrupts.
Pin change interrupts on PCINT15..0 are detected asynchronously. This means that these inter-
rupts can be used for waking the part also from sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge, or a low level. This is configured
as described in
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held
low. Low level and edge interrupts on INT0 are detected asynchronously. This implies that these
interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O
clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt.
If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no
interrupt will be generated and execution will continue from the instruction following the SLEEP
command. The start-up time is defined by the SUT and CKSEL fuses, as described in
Clock and Clock Options” on page
An example of timing of a pin change interrupt is shown in
• Pin Change Interrupt PCI0 triggers if a pin in PCINT7:0 is toggled while enabled
• Pin Change Interrupt PCI1 triggers if a pin in PCINT15:8 is toggled while enabled
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
;
0x0010
0x0011
0x0012
0x0013
...
RESET: ldi
...
<instr>
“MCUCR – MCU Control Register” on page
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
out
sei
...
xxx
...
TIM0_COMPA
TIM0_COMPB
TIM0_OVF
ANA_COMP
ADC
EE_RDY
USI_STR
USI_OVF
r16, low(RAMEND); Main program start
SPL,r16
23.
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; Timer0 Overflow Handler
; Analog Comparator Handler
; ADC Conversion Handler
; EEPROM Ready Handler
; USI Start Handler
; USI Overflow Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
Figure 10-1
59. When the INT0 interrupt is
below.
8048B–AVR–03/09
“System