ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 63
ATtiny43U
Manufacturer Part Number
ATtiny43U
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny43U
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
0.7 to 5.5
Operating Voltage (vcc)
0.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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11.2
11.2.1
8048B–AVR–03/09
Ports as General Digital I/O
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 11-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits are
accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn
bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
SLEEP
(1)
SYNCHRONIZER
D
L
Q
Q
D
PINxn
Q
Q
RESET
RESET
PORTxn
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Figure 11-2
PUD
WDx
RDx
RPx
clk
1
0
I/O
WRx
shows a func-
WPx
I/O
,
63
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