SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 1163

• Manufacturer Part Number: SAM9X35
• Manufacturer: Atmel Corporation

Specifications of SAM9X35

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.7.14
Name:
Address:
Access:
Reset:
• SOF: Start of Frame Interrupt Status Register
When set to one this flag indicates that a start of frame event has been detected. This flag is reset after a read operation.
• DIS: LCD Disable Interrupt Status Register
When set to one this flag indicates that the horizontal and vertical timing generator has been successfully disabled. This
flag is reset after a read operation.
• DISP: Power-up/Power-down Sequence Terminated Interrupt Status Register
When set to one this flag indicates whether the power-up sequence or power-down sequence has terminated. This flag is
reset after a read operation.
• FIFOERR: Output FIFO Error
When set to one this flag indicates that an underflow occurs in the output FIFO. This flag is reset after a read operation.
• BASE: Base Layer Raw Interrupt Status Register
When set to one this flag indicates that a Base layer interrupt is pending. This flag is reset as soon as the BASEISR register
is read.
• OVR1: Overlay 1 Raw Interrupt Status Register
When set to one this flag indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the OVR1ISR
register is read.
• HEO: High End Overlay Raw Interrupt Status Register
When set to one this flag indicates that a Hi End layer interrupt is pending. This flag is reset as soon as the HEOISR regis-
ter is read.
• HCR: Hardware Cursor Raw Interrupt Status Register
When set to one this flag indicates that a Hardware Cursor layer interrupt is pending. This flag is reset as soon as the
HCRISR register is read.
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
31
23
15
–
–
–
7
–
LCD Controller Interrupt Status Register
LCDC_LCDISR
0xF8038038
Read-only
0x00000000
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
FIFOERR
28
20
12
–
–
–
4
HCR
27
19
11
–
–
3
–
DISP
HEO
26
18
10
–
–
2
OVR1
DIS
25
17
–
–
9
1
SAM9X35
SAM9X35
BASE
SOF
24
16
–
–
8
0
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