SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 454
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 454 of 1325
- Download datasheet (30Mb)
Note: This field is found only in DDR2-SDRAM devices.
• EBISHARE: External Bus Interface is Shared
The DDR controller embedded in the EBI is used at the same time as another memory controller (SMC,..)
Reset value is 0.
0 = Only the DDR controller function is used.
1 = The DDR controller shares the EBI with another memory controller (SMC, NAND,..)
• ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y
Reset value is 0.
0 = After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read
access.
1 = After an ACTIVE command in Bank X, BURST STOP command cannot be issued to another bank to stop current read
access.
This field is unique to SDR-SDRAM, Low-power SDR-SDRAM and Low-power DDR1-SDRAM devices.
• NB: Number of Banks
The reset value is four banks.
Note: Only DDR-SDRAM 2 devices support eight internal banks.
• DECOD: Type of Decoding
The reset value is 0: sequential decoding.
0 = Sequential Decoding.
1 = Interleaved Decoding.
454
454
OCD
000
111
NB
0
1
SAM9X35
SAM9X35
OCD calibration mode exit, maintain setting
OCD calibration default
Number of banks
4
8
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
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