SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 32
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 32 of 1325
- Download datasheet (30Mb)
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Exception Modes and Handling
SAM9X35
SAM9X35
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep-
tions according to the following priority order:
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort
occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and pro-
ceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to
resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer
error does not escape detection.
Exceptions arise whenever the normal flow of a program must be halted temporarily, for exam-
ple, to service an interrupt from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
The register r13 is also banked across exception modes to provide each exception handler with
private stack pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable
nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in
the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies
according to the type of exception. This action restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or
remove the requirement for register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be
completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as
invalid, but does not take the exception until the instruction reaches the Execute stage in the
pipeline. If the instruction is not executed, for example because a branch occurs while it is in the
pipeline, the abort does not take place.
• Reset (highest priority)
• Data Abort
• FIQ
• IRQ
• Prefetch Abort
• BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
1. Preserves the address of the next instruction in the appropriate Link Register that cor-
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
responds to the new mode that has been entered. When the exception entry is from:
– ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction
– THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value
into LR (current PC(r15) + 4 or PC + 8 depending on the exception).
(current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the
program to resume from the correct place on return.
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
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