SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 291
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 291 of 1325
- Download datasheet (30Mb)
25.2.3
Table 25-3.
25.3
11055B–ATARM–22-Sep-11
0
1
2
3
4
5
6
7
8
9
Peripheral Bridge 0
Peripheral Bridge 1
USB Device High
USB Host OHCI
USB Host EHCI
Internal SRAM
Masters
Memory Mapping
Internal ROM
Slaves
External Bus
DDR2 Port 1
DDR2 Port 2
DDR2 Port 3
Speed DPR
Master to Slave Access
Interface
registers
registers
SMD
Master to Slave Access
ARM926
Instr.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table.
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each
AHB master several memory mappings. Each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM
or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR),
that performs remap action for every master independently.
0
X
X
X
X
X
X
X
X
-
-
ARM926
Data
1
X
X
X
X
X
X
X
X
-
-
DMA 0 DMA 1
2&3
X
X
X
X
X
X
-
-
-
-
4&5
X
X
X
X
X
X
X
-
-
-
Device HS
DMA
USB
6
X
X
-
-
-
-
-
-
-
-
USB Host
HS EHCI
7
X
X
-
-
-
-
-
-
-
-
USB Host
HS OHCI
8
X
X
-
-
-
-
-
-
-
-
LCD DMA EMAC DMA Reserved
9
X
X
X
-
-
-
-
-
-
-
SAM9X35
10
X
X
-
-
-
-
-
-
-
-
11
X
X
-
-
-
-
-
-
-
-
291
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