SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 1110

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

40.11.6
40.11.6.1
Table 40-48. SMC Read Signals - NRD Controlled (READ_MODE = 1)
1110
1110
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
1
2
3
4
5
6
7
SAM3S8/SD8
SAM3S8/SD8
SMC Timings
Parameter
Data Setup before NRD High
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
NCS low before NRD High
NRD Pulse Width
Read Timings
A0 - A22 Valid before NRD High
VDDIO Supply
Figure 40-28. Min and Max Access Time of Output Signals
SMC Timings are given with the following conditions.
VDDIO = 1.62V @ 30 pF
VDDIO = 3V @ 50 pF
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables t
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold = 0)
NO HOLD SETTINGS (nrd hold = 0)
TK (CKI =0)
TK (CKI =1)
HOLD SETTINGS (nrd hold ≠ 0)
nrd pulse - ncs
(nrd setup +
(nrd setup +
t
t
nrd pulse)*
nrd pulse *
CPMCK
rd setup) *
CPMCK
t
TF/TD
CPMCK
CPMCK
1.8V
27
25
0
0
+ 12
+ 12
(2)
- 5
is the MCK period. Timing extraction
Min
nrd pulse - ncs
t
(nrd setup +
(nrd setup +
CPMCK
t
nrd pulse)*
nrd pulse *
rd setup) *
CPMCK
t
CPMCK
3.3V
25.5
20.4
0
0
SSC
SSC
+ 10.5
(3)
+ 11
- 5
0max
0min
1.8V
(2)
Max
3.3V
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
(3)
Units
ns
ns
ns
ns
ns
ns
ns