SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 382

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

23.8.1.1
23.8.1.2
23.8.1.3
382
382
SAM3S8/SD8
SAM3S8/SD8
NRD Waveform
NCS Waveform
Read Cycle
Figure 23-5. Standard Read Cycle
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where
address is set on the address bus to the point where address may change. The total read cycle
time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the
falling edge;
rising edge;
rising edge.
the NCS falling edge.
NCS rising edge;
NCS rising edge.
A[23:0]
D[7:0]
MCK
NRD
NCS
NCS_RD_SETUP
NRD_SETUP
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
NRD_HOLD
NCS_RD_HOLD
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12