SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 736

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

32.7.8.2
32.7.8.3
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Baud Rate
Data Transfer
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous
mode:
some restrictions:
In SPI Master Mode:
In SPI Slave Mode:
Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge
(depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity
bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register
(US_MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The
MSB data bit is always sent first in SPI Mode (Master or Slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is
programmed with the CPOL bit in the Mode Register. The clock phase is programmed with the
CPHA bit. These two parameters determine the edges of the clock signal upon which data is
driven and sampled. Each of the two parameters has two possible states, resulting in four possi-
ble combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a dif-
ferent slave.
Table 32-15. SPI Bus Protocol Mode
• the external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD
• if the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be
• the external clock (SCK) selection is forced regardless of the value of the USCLKS field in the
• to obtain correct behavior of the receiver and the transmitter, the external clock (SCK)
to “1” in the Mode Register (US_MR), in order to generate correctly the serial clock on the
SCK pin.
must be superior or equal to 6.
even to ensure a 50:50 mark/space ratio on the SCK pin, this value can be odd if the internal
clock is selected (MCK).
Mode Register (US_MR). Likewise, the value written in US_BRGR has no effect, because
the clock is provided directly by the signal on the USART SCK pin.
frequency must be at least 6 times lower than the system clock.
See “Baud Rate in Synchronous Mode or SPI Mode” on page 709.
SPI Bus Protocol Mode
0
1
2
3
CPOL
0
0
1
1
SAM3S8/SD8
SAM3S8/SD8
However, there are
CPHA
1
0
1
0
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