SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 307

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

Figure 18-7. Example of Partial Page Programming
18.4.3.3
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
X words
X words
X words
X words
Erase Commands
So Page Y erased
Erase All Flash
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
32-bit wide
Step 1.
FF
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FF
FF
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FF
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FF
...
...
...
...
FF
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FF
Two errors can be detected in the EEFC_FSR register after a programming sequence:
By using the WP command, a page can be programmed in several steps if it has been erased
before (see
The Partial Programming mode works only with 128-bit (or higher) boundaries. It cannot be used
with boundaries lower than 128 bits (8, 16 or 32-bit for example).
Erase commands are allowed only on unlocked regions. Depending on the Flash memory, sev-
eral commands can be used to erase the Flash:
The erase sequence is:
Two errors can be detected in the EEFC_FSR register after a programming sequence:
• When programming is completed, the FRDY bit in the Flash Programming Status Register
• Command Error: a bad keyword has been written in the EEFC_FCR register.
• Lock Error: the page to be programmed belongs to a locked region. A command must be
• Erase all memory (EA): all memory is erased. The processor must not fetch code from the
• Erase a memory plane (EPL): all pages in the memory plane are erased in parallel. The
• Erase starts as soon as one of the erase commands and the FARG field are written in the
• When the programming completes, the FRDY bit in the Flash Programming Status Register
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
(EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR,
the corresponding interrupt line of the NVIC is activated.
previously run to unlock the corresponding region.
Flash memory.
processor must not fetch code from the erased Flash memory plane (only for SAM3SD8).
Flash Command Register.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR,
the interrupt line of the NVIC is activated.
Figure 18-7
Programming of the second part of Page Y
below).
FF
FF
FF
CA FE
CA FE
CA FE
FF
FF
FF
FF
FF
FF
32-bit wide
FF
FF
FF
FF
FF
FF
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FF
Step 2.
...
...
...
...
FF
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CA
CA
CA
FF
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FE
FE
FE
Programming of the third part of Page Y
FF
FF
FF
CA FE
CA FE
CA FE
DE CA
DE CA
DE CA
FF
FF
FF
SAM3S8/SD8
SAM3S8/SD8
32-bit wide
FF
FF
FF
FF
FF
FF
Step 3.
...
...
...
...
CA
CA
CA
FF
FF
FF
DE CA
DE CA
DE CA
FF
FF
FF
FF
FF
FF
FE
FE
FE
FF
FF
FF
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