LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 105
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
LPC1857_53
Manufacturer Part Number
LPC1857_53
Description
The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1853FBD208.pdf
(131 pages)
- Current page: 105 of 131
- Download datasheet (2Mb)
NXP Semiconductors
Table 17.
C
LPC1857_53
Objective data sheet
Symbol
Common to read and write cycles
t
t
t
t
t
t
t
d(SV)
h(S)
d(RASV)
h(RAS)
d(CASV)
h(CAS)
d(WV)
Fig 27. External static memory read/write access (PB = 1)
Fig 28. External static memory burst read cycle
L
= 30 pF, T
EMC_BLSx
EMC_CSx
EMC_BLSx
EMC_WE
EMC_OE
EMC_CSx
EMC_Ax
EMC_Dx
EMC_WE
EMC_OE
EMC_Ax
EMC_Dx
Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 1
amb
Parameter
chip select valid delay time
chip select hold time
row address strobe valid delay time
row address strobe hold time
column address strobe valid delay time
column address strobe hold time
write valid delay time
=
40
C to 85
C, V
RD
RD
DD(REG)(3V3)
RD
RD
2
5
3
1
RD
All information provided in this document is subject to legal disclaimers.
RD
5
5
RD
Rev. 1 — 14 December 2011
= <tbd>.
RD
5
RD
5
4
RD
5
EOR
Conditions
RD
RD
RD
6
7
7
WR
WR
RD
2
WR
5
3
32-bit ARM Cortex-M3 microcontroller
4
WR
WR
1
5
Min
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
WR
6
WR
RD
Typ
LPC1857/53
7
5
EOW
© NXP B.V. 2011. All rights reserved.
Max
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
002aag216
WR
002aag215
WR
8
8
105 of 131
Unit
ns
ns
ns
ns
ns
ns
ns
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