LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 75

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
7.16.6.1 Features
7.17.1.1 Features
7.16.6 C_CAN
7.17.1 General purpose 32-bit timers/external event counter
7.17 Counter/timers and motor control
Remark: The LPC1857/53 contain two C_CAN controllers.
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller supports powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a high level of reliability.
Remark: The LPC1857/53 include four 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an externally
supplied clock. It can optionally generate interrupts, generate timed DMA requests, or
perform other actions at specified timer values, based on four match registers. Each
timer/counter also includes two capture inputs to trap the timer value when an input signal
transitions, optionally generating an interrupt.
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Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
Provides programmable loop-back mode for self-test operation.
A 32-bit timer/counter with a programmable 32-bit prescaler.
Counter or timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event can also generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
© NXP B.V. 2011. All rights reserved.
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