LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 61

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
7.5.2 Interrupt sources
7.7.1 Features
7.6 Event router
7.7 Global Input Multiplexer Array (GIMA)
7.8 On-chip static RAM
7.9 On-chip flash memory
Each peripheral device has one interrupt line connected to the NVIC but can have several
interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
The event router combines various internal signals, interrupts, and the external interrupt
pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event
router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,
Deep-sleep, Power-down, and Deep power-down modes. Individual events can be
configured as edge or level sensitive and can be enabled or disabled in the event router.
The event router can be battery powered.
The following events if enabled in the event router can create a wake-up signal and/or an
interrupt:
The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers,
event router, or the ADCs.
The LPC1857/53 support up to136 kB SRAM with separate bus master access for higher
throughput and individual power control for low power operation.
The LPC1857/53 contain up to 1 MB of dual-bank flash program memory. With dual-bank
flash memory, the user code can write or erase one flash bank while reading the other
flash bank without interruption. A two-port flash accelerator maximizes the flash
performance.
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Non-Maskable Interrupt (NMI).
Software interrupt generation.
External pins WAKEUP0/1/2/3 and RESET
Alarm timer, RTC, WWDT, BOD interrupts
C_CAN0/1 and QEI interrupts
Ethernet, USB0, USB1 signals
Selected outputs of combined timers (SCT and timer0/1/3)
Single selection of a source.
Signal inversion.
Can capture a pulse if the input event source is faster than the target clock.
Synchronization of input event and target clock.
Single-cycle pulse generation for target.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
© NXP B.V. 2011. All rights reserved.
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