LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 62

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 4.
LPC1857_53
Objective data sheet
Boot mode BOOT_SRC
Pin state
USART0
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
Boot mode when OTP BOOT_SRC bits are programmed
bit 3
0
0
0
0
0
0
7.10 EEPROM
7.11 Boot ROM
In-System Programming (ISP) and In-Application Programming (IAP) routines for
programming the flash memory are provided in the Boot ROM.
The LPC1857/53 contain up to 16 kB of on-chip byte-erasable and byte-programmable
EEPROM memory.
The internal ROM memory is used to store the boot code of the LPC1857/53. After a
reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
AES capable parts also support:
The default boot source is the flash memory. Several other boot modes are available
depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not
programmed or the BOOT_SRC bits are all zero, the states of the boot pins P2_9, P2_8,
P1_2, and P1_1 determine the boot mode.
•
•
•
•
•
•
•
•
BOOT_SRC
bit 2
0
0
0
0
1
1
ROM memory size is 64 kB.
Supports booting from USART interfaces (in UART mode) and external static memory
such as NOR flash, SPI flash, quad SPI flash.
Includes APIs for power control and OTP programming.
Includes SPIFI drivers.
Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.
CMAC authentication on the boot image.
Secure booting from an encrypted image. In development mode booting from a plain
text image is possible. Development mode is terminated by programming the AES
key.
API for AES programming.
All information provided in this document is subject to legal disclaimers.
BOOT_SRC
bit 1
0
0
1
1
0
0
Rev. 1 — 14 December 2011
BOOT_SRC
bit 0
0
1
0
1
0
1
Description
The reset state of P1_1, P1_2, P2_8, and P2_9
pins determines the boot source. See
P2_0 and P2_1.
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
Boot from device connected to USART0 using pins
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
© NXP B.V. 2011. All rights reserved.
Table
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5.