LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 74

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
7.16.4.1 Features
7.16.5.1 Features
7.16.5 I
Remark: The LPC1857/53 contain two I
The I
The I
and one word select signal. The basic I
always the master, and one slave. The I
receive channel, each of which can operate as either a master or a slave.
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S interface
I
supports Fast mode plus with bit rates up to 1 Mbit/s.
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
All I
The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,
96, 192) kHz.
Support for an audio master clock.
Configurable word select period in master mode (separately for I
output).
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. The DMA requests are
connected to the GPDMA block.
Controls include reset, stop and mute options separately for I
output.
2
2
2
2
C0 is a standard I
C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I
S-bus provides a standard communication interface for digital audio applications.
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
2
C-bus controllers support multiple address recognition and a bus monitor mode.
2
C-bus can be used for test and diagnostic purposes.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
2
C-bus compliant bus interface with open-drain pins. I
2
2
2
S-bus connection has one master, which is
S-bus interface provides a separate transmit and
S interfaces.
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
2
S-bus input and I
2
S-bus input and
2
© NXP B.V. 2011. All rights reserved.
C-bus).
2
C0 also
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2
S-bus