LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 68

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
7.15.2.1 Features
7.15.2 General-Purpose DMA (GPDMA)
7.15.3 SPI Flash Interface (SPIFI)
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral for
master 1, but only memory for master 0.
The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM
Cortex-M3 processor with little performance penalty compared to parallel flash devices
with higher pin count.
After a few commands configure the interface at startup, the entire flash content is
accessible as normal memory using byte, halfword, and word accesses by the processor
and/or DMA channels. Simple sequences of commands handle erasure and
programming.
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Eight DMA channels. Each channel can support a unidirectional transfer.
16 DMA request lines.
Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
Scatter or gather DMA is supported by using linked lists. This means that the source
and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority.
AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
Two AHB bus masters for transferring data. These interfaces transfer data when a
DMA request goes active. Master 1 can access memories and peripherals, master 0
can access memories only.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
Internal four-word FIFO per channel.
Supports 8, 16, and 32-bit wide transactions.
Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
before to masking.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
© NXP B.V. 2011. All rights reserved.
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