LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 59

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
LPC1857_53
Objective data sheet
7.1 Architectural overview
7.2 ARM Cortex-M3 processor
7.3 System Tick timer (SysTick)
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus. The I-code and D-code core buses allow for concurrent code and data
accesses from different slave ports.
The LPC1857/53 use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and
other bus masters to peripherals. Flexible connections allow different bus masters to
access peripherals that are on different slave ports of the matrix simultaneously.
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and low power consumption. The ARM Cortex-M3 offers many new features,
including a Thumb-2 instruction set, low interrupt latency, hardware multiply and divide,
interruptable/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual.
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
© NXP B.V. 2011. All rights reserved.
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