LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 73

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
7.16.2.1 Features
7.16.3.1 Features
7.16.3 SSP serial I/O controller
7.16.4 I
Remark: The LPC1857/53 contain two SSP controllers.
The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
Remark: The LPC1857/53 each contain two I
The I
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example, an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
multi-master bus and can be controlled by more than one bus master connected to it.
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C-bus interface
Maximum UART data bit rate of <tbd> MBit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
Support for RS-485/9-bit/EIA-485 mode.
USART3 includes an IrDA mode to support infrared communication.
All USARTs have DMA support.
Support for synchronous mode.
Smart card mode conforming to ISO7816 specification
Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
Connected to the GPDMA
2
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
2
C-bus controllers.
32-bit ARM Cortex-M3 microcontroller
2
C-bus interface is a
LPC1857/53
© NXP B.V. 2011. All rights reserved.
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