LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 63

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
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LPC1857_53
Objective data sheet
Table 4.
Boot mode BOOT_SRC
USB0
USB1
SPI (SSP)
USART3
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Boot mode when OTP BOOT_SRC bits are programmed
bit 3
0
0
1
1
Table 5.
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Boot mode
USART0
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
USB0
USB1
SPI (SSP)
USART3
BOOT_SRC
bit 2
1
1
0
0
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Boot mode when OPT BOOT_SRC bits are zero
All information provided in this document is subject to legal disclaimers.
BOOT_SRC
bit 1
1
1
0
0
Pins
P2_9
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
Rev. 1 — 14 December 2011
P2_8
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
BOOT_SRC
bit 0
0
1
0
1
P1_2
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
Description
Boot from USB0.
Boot from USB1.
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8
P2_3 and P2_4.
Boot from device connected to USART3 using pins
P1_1
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
32-bit ARM Cortex-M3 microcontroller
Description
Boot from device connected to USART0
using pins P2_0 and P2_1.
Boot from Quad SPI flash connected to
the SPIFI interface on P3_3 to P3_8
Boot from external static memory (such
as NOR flash) using CS0 and an 8-bit
data bus.
Boot from external static memory (such
as NOR flash) using CS0 and a 16-bit
data bus.
Boot from external static memory (such
as NOR flash) using CS0 and a 32-bit
data bus.
Boot from USB0
Boot from USB1.
Boot from SPI flash connected to the
SSP0 interface on P3_3, P3_6, P3_7
and P3_8
Boot from device connected to USART3
using pins P2_3 and P2_4.
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LPC1857/53
© NXP B.V. 2011. All rights reserved.
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