LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 81
LPC1857_53
Manufacturer Part Number
LPC1857_53
Description
The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1853FBD208.pdf
(131 pages)
- Current page: 81 of 131
- Download datasheet (2Mb)
NXP Semiconductors
LPC1857_53
Objective data sheet
Fig 8.
LPC1857/53 Power domains
USB0_VDDA3V3_DRIVER
7.20.10 Code security (Code Read Protection - CRP)
USB0_VDDA3V3
The LPC1857/53 support four reduced power modes: Sleep, Deep-sleep, Power-down,
and Deep power-down.
The LPC1857/53 can wake up from Deep-sleep, Power-down, and Deep power-down
modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in
the RTC power domain.
CRP enables different levels of security so that access to the on-chip flash and use of the
JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by CRP.
VDDREG
RTCX1
RTCX2
VDDIO
VDDA
VSSA
VBAT
VPP
VSS
LPC18xx
All information provided in this document is subject to legal disclaimers.
USB0 POWER DOMAIN
OTP POWER DOMAIN
ALWAYS-ON/RTC POWER DOMAIN
ADC POWER DOMAIN
MAIN POWER DOMAIN
SELECTOR
OSCILLATOR
Rev. 1 — 14 December 2011
POWER
to I/O pads
32 kHz
to RTC I/O
pads (V
REGULATOR
ps )
ULTRA LOW-POWER
REGULATOR
OTP
USB0
BACKUP REGISTERS
DAC
ADC
REAL-TIME CLOCK
RESET/WAKE-UP
CONTROL
32-bit ARM Cortex-M3 microcontroller
to core
to memories,
peripherals,
oscillators,
PLLs
to RTC
domain
peripherals
002aag305
LPC1857/53
RESET
WAKEUP0/1/2/3
ALARM
© NXP B.V. 2011. All rights reserved.
81 of 131
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