MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 110

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

Interrupt Priorities and Vector Tables
102
VAB[0–5]
0x8-0x1F
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
Interrupt Number
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
60–63
57
58
59
OVERFLOW
DEFAULT
DEFAULT
ILLEGAL
DEBUG
Signal
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
TRAP
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
NMI
IRQ
—
—
—
Table 7-2. SIC and SIC_EXT Interrupt Vectors (Continued)
*Not supported in the MSC8101
*Not supported in the MSC8101
MSC8101 Programmer’s Quick Reference
Internal exception (generated by trap instruction)
External IRQ2 (edge/level configurable)
Bus controller (non-aligned data error)
Table 7-3. PIC Interrupt Vectors
HDI16 (4): External HOST command
EFCOP (3): Output FIFO not empty
HDI16 (1): Receive FIFO not empty
HDI16 (3): Transmit FIFO not full
Bus controller (level1 contention)
HDI16 (2): Transmit FIFO empty
EFCOP (0): Input FIFO not full
Bus controller (p-x contention)
EFCOP (1): Input FIFO empty
Bus controller (x-y contention)
EFCOP (2): Output FIFO full
HDI16 (0): Receive FIFO full
In VAB disabled mode only*
In VAB disabled mode only*
Overflow exception (DALU)
Debug exception (EOnCE)
EFCOP (4): Update done
Illegal instruction or set
Description
Reserved
Description
PC6
PC5
PC4
Reserved
Reserved
Reserved
Reserved
0b11_1100–0b11_1111
Service Routine Address
Interrupt Vector
(Offset from VBA)
0b11_1001
0b11_1010
0b11_1011
0x200–0x7FF
0xAC0
0xBC0
0x1C0
0x8C0
0x9C0
0xA00
0xA40
0xA80
0xB00
0xB40
0xB80
0x100
0x140
0x180
0x800
0x840
0x880
0x900
0x940
0x980
0xC0
0x40
0x80
0x0