MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 70

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

HOTX
HORX
ICR
ICR
ICR
ICR
11–12 HF[2–3]
9–10 HM/HDM[0–2]
Bits
5–6
Type
Type
13
8
Bit
Bit
Bit
Bit
A four 64-bit word FIFO. If HOTX is empty, writing it clears HSR[HTFE]. If HOTX contains three 64-bit words, writing it clears HTFNF.
A four 64-bit word FIFO. If HORX is full, reading it clears HSR[HRFF]. If HORX contains one 64-bit word, reading it clears HSR[HRFNE].
Host Interface Control Register (DMA = 0, HICR = 1)
Host Interface Control Register (DMA = 1, HICR = 1)
Host Interface Control Register (DMA = 0, HICR = 0)
Host Interface Control Register (DMA = 1, HICR = 0)
Notes:
HF[0–1]
INIT
HDRQ
0
0
0
0
Name
1. HDM0 when read, TREQ when written.
Host Transmit Data Register
Host Receive Data Register
1
1
1
1
Host Flags 0–1
Force Initialization
Host Mode/Host DMA Mode
Host Flags 2–3
HREQ/HTRQ and HACK/HRRQ Pin Control
(Available only in non-DMA [interrupt] mode)
—
—
—
—
2
2
2
2
3
3
3
3
R/W
R/W
Description
4
4
4
4
Table 6-5. HDI16 Registers (Continued)
HF0
HF0
HF0
HF0
5
5
5
5
HF1
HF1
HF1
HF1
ICR Bit Descriptions
Reset:: Depends on reset configuration sequence
Reset:: Depends on reset configuration sequence
Reset:: Depends on reset configuration sequence
Reset:: Depends on reset configuration sequence
6
6
6
6
—
—
—
—
7
7
7
7
Host can set or clear; these bits are reflected in the HSR[HF] bits.
Host can set, then HDI16 runs the INIT command and clears the INIT bit.
See information on host DMA mode control values in the MSC8101
Reference Manual.
Host can set or clear; these bits are reflected in the HSR[HF] bits.
0 = HREQ and HACK
1 = HTRQ and HRRQ
INIT
INIT
INIT
INIT
8
8
8
8
2.
9
9
9
9
HDM0 when read, RREQ when written.
HDM
HDM
HM
HM
R
R
10
10
10
10
HF2
HF2
HF2
HF2
11
11
11
11
Settings
HF3
HF3
HF3
HF3
12
12
12
12
Type: R/W
Type: R/W
Type: W
Type: R
HDRQ
HDRQ
R/W
R/W
13
13
—
13
13
—
Note 1
TREQ
TREQ
TREQ
14
14
14
14
0x00A0
Note 2
0x0080
RREQ
RREQ
RREQ
15
15
15
15
0x0
0x0
0x0
0x0