MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 128
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MSC8101PG
Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MSC8101PG.pdf
(162 pages)
- Current page: 128 of 162
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BREAK
BSR
BSRD
BT
BTD
CLB
CLR
CMPEQ
Mnemomic
Terminate the loop and branch to an address
PC + displacement
0
Branch to subroutine
(Next PC)
PC + displacement
Branch to subroutine (delayed)
(4 cycles minus time for delay slot, but not less than 2 cycles.)
(Next PC)
PC + displacement
Branch if true (Not taken: 1 cycle; taken: 4.)
If T==1, then PC + displacement
If T==1, then PC + displacement
Count leading bits (ones or zeros)
If Da[39] == 0,
Clear
0
Compare for equal
If Da = = Dn, then 1
Branch if true (delayed)
then 9 – (number of consecutive leading
zeros in Da[39:0])
else 9 – (number of consecutive leading
ones in Da[39:0])
LFn
Dn
(SP); SR
(SP); SR
Operation
PC
PC
PC
Dn
T, else 0
Dn
(SP + 4); SP + 8
(SP + 4); SP + 8
(4 cycles minus time for delay slot, but not less than 1 cycle.)
Table 9-5. Instructions Grouped Alphabetically (Continued)
T
PC
PC
Description
SP;
SP;
BREAK label
BSR <label
BSR >label
BSRD <label
BSRD >label
BT <label
BT >label
BTD <label
BTD >label
CLB Da,Dn
CLR Dn
CMPEQ Da,Dn
Assembler Syntax
Words
2
1
2
1
2
1
2
1
2
1
1
1
Cycles
1/4
1/4
1/4
1/4
4
4
4
4
4
1
1
1
Type
4
4
4
4
4
4
4
4
4
2
1
1
Functional
Change-of-
Change-of-
Change-of-
Change-of-
Arithmetic
Arithmetic
Logical
Group
DALU
DALU
DALU
Loop
Flow
Flow
Flow
Flow
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