MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 97
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MSC8101PG
Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MSC8101PG.pdf
(162 pages)
- Current page: 97 of 162
- Download datasheet (2Mb)
MPTPR
DCHCRx
10–15 BDPTR
Reset
Bits
5–7
Addr
16
0
1
8
9
Bit
Bit
Bit
Notes:
ACTV
PPC
EXP
DRS
DPL
DRACK
DRACK
ACTV
16
(DCHCR3) 0x1070C
0
0
(DCHCR0) 0x10700
(DCHCR1) 0x10704
(DCHCR2) 0x10708
0
Name
Memory Refresh Timer Prescaler Register
1. Where x can be a zero or a one—that is, 0000_0010 or 0000_0011
DMA Channel Configuration Registers
PPC
FLY
17
1
0
1
Active DMA Channel x
PowerPC Bus
Expiration Timer
DREQ Sensitivity Mode
DREQ Polarity
Buffer Pointer
DRACK Protocol
PTP (Memory Timers Prescaler)
18
—
2
0
2
19
3
0
—
3
20
Description
4
0
(DCHCR7) 0x1071C
(DCHCR4) 0x10710
(DCHCR5) 0x10714
(DCHCR6) 0x10718
Table 6-12. Memory Controller Registers (Continued)
4
RQNUM
5
0
21
5
Table 6-13. DMA Registers
DCHCRx Bit Descriptions
EXP
6
1
22
6
7
23
x
7
0 = Disabled
0 = Channel assigned to PowerPC Local bus
1 = Assigned to PowerPC 60x bus
Channel ignores EXP+1 bus cycles
0 = DREQ edge-triggered
0 = Active high or rising edge-triggered
1 = Active low or falling edge-triggered
Pointer to the line in the DCPRAM assigned to this channel
0 = Channel does not use DRACK
DRS
FRZ
(DCHCR11) 0x1072C
8
0
(DCHCR10) 0x10728
24
(DCHCR8) 0x10720
(DCHCR9) 0x10724
8
Reset: 0
DPL
INT
9
0
25
9
10
0
10
26
—
11
0
11
27
Settings
—
1 = Enabled
1 = DREQ level-triggered
1 = Channel uses DRACK
12
0
(DCHCR15) 0x1073C
(DCHCR12) 0x10730
(DCHCR13) 0x10734
(DCHCR14) 0x10738
12
28
Type: R/W
Type: R/W
BDPTR
13
13
29
0
PRIO
14
30
14
0
0x10184
15
31
15
0
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