MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 22

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

External Signals
14
BNKSEL[0–2]
MODCK[1–3]
THERM[1–2]
PORESET
RSTCONF
HRESET
SRESET
TC[0–2]
DBREQ
CLKIN
Name
TDO
HPE
EE0
EE1
Input/Output Hard Reset
Input/Output Soft Reset
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Data
Table 3-1. External Signals–SIU and Extended Core (Continued)
—
Test Data Out (JTAG)
Data output from the MSC8101 JTAG/COP controller.
Power-On Reset
When asserted, this input line causes the MSC8101 to enter power-on reset state.
Reset Configuration
Used during the reset configuration sequence of the chip. For a detailed explanation of
its function, see Section 5.1.1, Power-On Reset Flow, and Section 5.2, Hardware
Reset Configuration, of the MSC8101 Reference Manual.
When asserted, this open-drain line causes the MSC8101 to enter hard reset state.
When asserted, this open-drain line causes the MSC8101 to enter soft reset state.
Clock In
Primary clock input to the MSC8101 PLL.
Clock Modes 1–3
Define the operating mode of internal clock circuits.
Bank Select 0–2
Select the SDRAM bank when the MSC8101 is in 60x-compatible bus mode. BNKSELx
is the msb of the three BNKSEL signals.
Transfer Code 0–2
Supply information for debug purposes for each of the bus transactions initiated by the
MSC8101.
Leave disconnected.
Debug Request
Determines whether to go immediately into SC140 Debug mode when PORESET is
deasserted.
Enhanced OnCE (EOnCE) Event 0
After PORESET is deasserted, you can configure EE0 as an input (default) or an output.
See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for
details on how to configure this pin.
Debug request, enable Address Event Detection Channel 0, or generate one of the
EOnCE events.
Detection by Address Event Detection Channel 0. Used to trigger external debugging
equipment.
Host Port Enable
When this pin is asserted during PORESET, the Host port is enabled, the PowerPC 60x
data bus is 32 bits wide, and the Host must program the reset configuration word.
EOnCE Event 1
After PORESET is deasserted, you can configure EE1 as an input (default) or an output.
See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for
details on how to configure this pin.
Enable Address Event Detection Channel 1 or generate one of the EOnCE events.
Debug Acknowledge or detection by Address Event Detection Channel 1. Used to
trigger external debugging equipment.
MSC8101 Programmer’s Quick Reference
Description