MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 61

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

6
6.1
R[0–15]
NSP, ESP
B[0–7]
N[0–3]
M[0–3]
MCTL
D[0–15]
PC
SR
EMR
SA[0–3]
LC[0–3]
Convention
R/W
Registers
Mnemonic
W
R
Core Registers
Read-only bit. Writing this bit has no effect.
Write-only bit.
Standard read/write bit.
Address
Shadow stack pointer
Base address
Offset
Modifier
Modifier control
Data
Exception and mode
Start address
Loop counter
Stack pointer
Program counter
Status
Register Name
Meaning
Table 6-1. Register Description Conventions
32-bit, R/W. Contain addresses or general-purpose data
32-bit. Used implicitly in all PUSH and POP instructions: NSP in Normal mode, ESP in Exception mode
Contain decremented values of the stack pointers
32-bit, R/W. Used in modulo calculations and associated with R registers (B0 with R0, and so on)
32-bit, R/W. Contain offset values to increment or decrement address registers. Also used for 32-bit
general-purpose storage
32-bit, R/W. Contain the value of the modulus modifier. Also used for general-purpose storage
32-bit, R/W. Programs the address mode for each address, R[0–7]
40-bit. Used to perform arithmetic and logical operations on data operands
32-bit
32-bit. Reflects and controls exception situations in the core
Table 6-2. Core Registers Summary
Convention
—
0
1
Reserved bit. Write to zero for future compatibility
Bit resets to a logic 0
Bit resets to a logic 1
Description
Meaning