MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 157

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

Index
Numerics
60x Address Acknowledge (AACK) signal 7
60x Address Bus (A[0-31]) signal 6
60x Address Bus Busy (ABB) signal 7
60x Address Retry (ARTRY) signal 7
60x Bus Arbiter Configuration Register 69
60x Bus Arbitration-Level Register 70
60x Bus Grant (BG) signal 6
60x Bus Output Enable (POE) signal 13
60x Bus Parity Byte Select (PPBS) signal 13
60x Bus Request (BR) signal 6
60x Bus SDRAM A10 (PSDA10) signal 12
60x Bus SDRAM Address Multiplexer (PSDAMUX)
60x Bus SDRAM Channel Associated Signalling
60x Bus SDRAM DQM (PSDDQM[0-7]) signals 12
60x Bus SDRAM Ras (PSDRAS) signal 13
60x Bus SDRAM Write Enable (PSDWE) signal 13
60x Bus Transfer Burst (TBST) signal 6
60x Bus Transfer Error Status and Control Register 1 74
60x Bus Transfer Error Status and Control Register 2 74
60x Bus Transfer Start (TS) signal 7
60x Bus Transfer Type (TT[0-4]) signal 6
60x Bus UPM Byte Select (PBS[0-7]) signals 12
60x Bus User-Programmable Memory General-Purpose
60x Bus User-Programmable Memory General-Purpose
60x Bus User-Programmable Memory General-Purpose
60x Bus User-Programmable Memory General-Purpose
60x Bus User-Programmable Memory General-Purpose
60x Bus User-Programmable Memory General-Purpose
60x Bus User-Programmable Memory
60x Bus Write Enable (PWE[0-7]) signal 12
60x Bus-Assigned SDRAM Refresh Timer Register 88
60x Bus-Assigned UPM Refresh Timer Register 88
60x Data Bus Bit 52 (52) signal 8
60x Data Bus Bit 53 (53) signal 8
60x Data Bus Bit 54 (D54) signal 8
60x Data Bus Bit 55 (D55) signal 8
60x Data Bus Bit 56 (D56) signal 9
signal 13
(PSDCAS) signal 13
Line 0 (PGPL0) signal 12
Line 1 (PGPL1) signal 13
Line 2 (PGPL2) signal 13
Line 3 (PGPL3) signal 13
Line 4 (PGPL4) signal 13
Line 5 (PGPL5) signal 13
Wait(PUPMWAIT) signal 13
MSC8101 Programmer’s Quick Reference
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71
,
74
60x Data Bus Bit 57 (D57) signal 9
60x Data Bus Bit 58 (D58) signal 9
60x Data Bus Bit 59 (D59) signal 9
60x Data Bus Bit 60 (D60) signal 9
60x Data Bus Bits 32-47 (D[0-31] ) signals 7
60x Data Bus Bits 48-51 (D[48-51] ) signals 8
60x Data Bus Bits 61-63 (D[61-63]) signal 9
60X Data Bus Busy (DBB) signal 7
60x Data Bus Grant (DBG) signal 7
60x Data Bus Most Significant Word (D[0-31]) signal 7
60x Data Parity 0 (DP0) signal 9
60x Data Parity 1 (DP1) signal 10
60x Data Parity 2 (DP2) signal 10
60x Data Parity 3 (DP3) signal 10
60x Data Parity 4 (DP4) signal 10
60x Data Parity 5 (DP5) signal 11
60x Data Parity 6 (DP6) signal 11
60x Data Parity 7 (DP7) signal 11
60x Data Valid (PSDVAL) signal 12
60x General-Purpose Chip-Select Machine Transfer
60x SDRAM Protocol-Specific Mode Register 85
60x Transfer Size (TSIZ[0-3]) signal 6
A
Address Latch Enable (ALE) signal 12
B
Bank Select 0-2 (BNKSEL[0-2]) signals 14
Base Registers 82
Baud-rate generator (BRG)
BCR Register 68
BD_ATTTR 92
Boot Mode 0-1 (BTM[0-1]) signals 15
BRx Registers 82
Buffer Attributes Parameter 92
Buffer Control 0 (BCTL0) signal 12
Buffer Control 1 (BCTL1) signal 12
Burst Address 27-28 (BADDR[27-28]) signals 12
Burst Address 29-31 (BADDR[29-31]) signals 6
Bus Configuration Register 68
C
Chip Select(CS[0-7]) signal 12
Clock In (CLKIN) signal 14
Achnowledge (PGTA) signal 13
memory map 46
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