MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 94

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MSC8101PG

Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
11–13 SDA10
14–16 RFRC
17–19 PRETOACT
20–22 ACTTORW
24–25 LDOTOPRE
26–27 WRC
30–31 CL
8–10 BSMA
5–7
23
28
29
SDAM
BL
EAMUX
BUFCMD
Address Multiplex Size
Bank Select Multiplexed Address Line
“A10” Control
Refresh Recovery (recovery interval in clock cycles)
Precharge to Activate Interval (clock-cycle wait states)
Activate to Read/Write Interval (clock-cycle wait states)
Burst Length
Last Data Out to Precharge (in clock cycles)
Write Recovery Time (in clock cycles)
External Address Multiplexing Enable/Disable
Command Buffer
CAS Latency
Table 6-12. Memory Controller Registers (Continued)
SDRAM Device-Specific Parameters:
SDAM
000
001
010
011
100
101
000 = A12–A14
001 = A13–A15
010 = A14–A16
011 = A15–A17
For PBI = 0:
000 = A12
001 = A11
010 = A10
011 = A9
000 = Reserved
001 = 3
001 = 1
001 = 1
0 = 4 (for device port size 64 or 16)
00 = 0
01 = 1
0 = Disabled (fastest timing)
1 = Enabled. Memory controller asserts SDAMUX for an extra cycle before
0 = Normal timing for control lines
1 = All control lines except CS are asserted for two cycles
00 = Reserved
issuing an
ACTIVATE
External. PowerPC Bus
Addr Pin
A13–A31
A14–A31
A15–A31
A16–A31
A17–A31
A18–A31
100 = A8
101 = A7
110 = A6
111 = A5
010 = 4
011 = 5
010 = 2
010 = 2
01 = -1
10 = 2
01 = 1
command to the SDRAM
100 = A16–A18
101 = A17–A19
110 = A18–A20
111 = A19–A21
For PBI = 1:
000 = A10
001 = A9
010 = A8
011 = A7
100 = 6
101 = 7
111 = 7
111 = 7
1 = 8 (for device port size 32 or 8)
10 = -2
11 = 3
10 = 2
Signal on External Pin
A5–A23
A5–A22
A5–A21
A5–A20
A5–A19
A5–A18
11 = Reserved
100 = A6
101 = A5
110 = A4
111 = A3
110 = 8
111 = 16
000 = 8
000 = 8
00 = 4
11 = 3

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