MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 15

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

HD[0–15]
D[32–47]
D[0–31]
ARTRY
AACK
Name
IRQ2
IRQ3
ABB
DBG
DBB
TS
Input/Output
Input/Output 60x Bus Transfer Start
Input/Output 60x Address Acknowledge
Input/Output
Input/Output
Input/Output 60x Data Bus Most Significant Word
Input/Output
Input/Output
Direction
Output
Output
Output
Input
Input
Input
Input
Input
Input
Data
Table 3-1. External Signals–SIU and Extended Core (Continued)
60x Address Bus Busy
The MSC8101 asserts this pin for the duration of the address bus tenure. Following an
address acknowledge (AACK) signal, which terminates the address bus tenure, the
MSC8101 negates ABB for a fraction of a bus cycle and then stops driving this pin.
The MSC8101 does not assume PowerPC 60x bus ownership as long as it senses that
this pin is asserted by an external 60x bus master.
Interrupt Request 2
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Signals the beginning of a new address bus tenure. The MSC8101 asserts this signal
when one of its internal 60x bus masters (SC140 core or DMA) begins an address
tenure. When the MSC8101 senses this pin being asserted by an external 60x bus
master, it responds to the address bus tenure as required (snoop if enabled, access
internal MSC8101 resources, memory controller support).
A 60x bus slave asserts this signal to indicate that it identified the address tenure.
Assertion of this signal terminates the address tenure.
60x Address Retry
Assertion of this signal indicates that the bus transaction should be retried by the 60x
bus master. The MSC8101 asserts this signal to enforce data coherency with its internal
cache and to prevent deadlock situations.
60x Data Bus Grant
An output when an internal arbiter is used. The MSC8101 asserts this pin as an output
to grant 60x data bus ownership to an external PowerPC bus master.
An input when an external arbiter is used. The external arbiter should assert this pin as
an input to grant 60x data bus ownership to the MSC8101.
60X Data Bus Busy
The MSC8101 asserts this pin as an output for the duration of the data bus tenure.
Following a TA, which terminates the data bus tenure, the MSC8101 negates DBB for a
fraction of a bus cycle and then stops driving this pin.
The MSC8101 does not assume PowerPC 60x data bus ownership as long as it senses
DBB is asserted by an external 60x bus master.
Interrupt Request 3
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
In write transactions the 60x bus master drives the valid data on this bus. In read
transactions the 60x slave drives the valid data on this bus. In Host Port Disabled mode,
these 32 bits are part of the 64-bit PowerPC data bus. In Host Port Enabled mode, these
bits are used as the PowerPC bus in 32-bit mode.
60x Data Bus Bits 32–47
In write transactions the 60x bus master drives the valid data on this bus. In read
transactions the 60x slave drives the valid data on this bus.
Host Data
When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional
tri-state data bus.
MSC8101 Programmer’s Quick Reference
Description
External Signals
7