HFC-S Cologne Chip AG, HFC-S Datasheet - Page 10

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HFC-S

Manufacturer Part Number
HFC-S
Description
Isdn S/t HDLC Basic Rate Controller
Manufacturer
Cologne Chip AG
Datasheet

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2.8
2.9
2.10
March 1997
19, 30, 41, 89, 42, 51, 61, 84
20, 29, 33, 39, 40, 47, 52, 62,
73, 81, 90, 93
Pin No.
All power supply pins VDD and GND must be directly connected to each other.
To keep VDD and GND bounce to a minimum a bypass capacitor (10 nF to 100 nF) should be
placed between each pair of VDD/GND pins.
100
94
95
96
97
98
99
49
important!
1)
2)
Interrupt outputs
Miscellaneous pins
Power supply
open drain, external pull up resistor required
open source, external pull down resistor required
IRQ_A
/IRQ_P
IRQ_B
IRQ_P
IRQ_C
/WD_RES
IRQ_D
WD_RES
IRQ_E
DMARQ0
IRQ_F
DMARQ1
NC
RESET
Pin No.
Pin Name
Tristate
Output
Input
OT
OT
OT
OT
OT
OT
OT
OT
OT
OT
O
O
I
VDD
GND
1)
2)
1)
2)
Pin Name
1
2,3,4
1
2,3,4
1
2,3,4
1
2,3,4
1
2,3,4
1
2,3,4
all
Mode Function
PC bus interrupt request A
processor interrupt request low active
PC bus interrupt request B
processor interrupt request high active
PC bus interrupt request C
Watchdog expired, external reset low active
PC bus interrupt request D
Watchdog expired, external reset high active
PC bus interrupt request E
DMA request AUX1 channel register (high active)
PC bus interrupt request F
DMA request AUX2 channel register (high active)
No connection (leave pin open)
Reset for HFC-S (high active)
Function
VDD (+3V to +5V)
GND
10 of 57
HFC-S

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