HFC-S Cologne Chip AG, HFC-S Datasheet - Page 49

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

8.2
Table 6: Activation/deactivation layer 1 for finite state matrix for TE
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Notes
Note 1: After reset the state machine is fixed to F0.
Note 2: This event reflects the case where a signal is received and the TE has not (yet) determined
Note 3: Bit- and frame-synchronisation achieved.
Note 4: Loss of Bit- or frame-synchronisation.
Note 5: Timer 3 (T3) is not implemented in the HFC-S and must be implemented in software.
March 1997
Event
State machine release
(Note 1)
Activate
Request
Expiry T3
(Note 5)
Receiving INFO 0
Receiving any signal
(Note 2)
Receiving INFO 2
(Note 3)
Receiving INFO 4
(Note 3)
Lost framing
(Note 4)
Activation/deactivation layer 1 for finite state matrix for TE
No change, no action
Impossible by the definition of the layer 1 service
Impossible situation
wether it is INFO 2 or INFO 4.
Receiving any signal
Receiving INFO 0
State number
State name
sent
Info
INFO 0
Reset
F0
F2
Sensing
INFO 0
F2
F3
F6
F7
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Deactivated
INFO 0
F3
F5
F4
F6
F7
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Awaiting
INFO 1
signal
F4
F3
F5
F6
F7
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Identifying
INFO 0
input
F5
F3
F6
F7
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Synchronized
INFO 3
F6
F3
F3
F7
F8
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Activated
INFO 3
F7
F3
F6
F8
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HFC-S
framing
INFO 0
Lost
F8
F3
F6
F7
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