HFC-S Cologne Chip AG, HFC-S Datasheet - Page 22

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

HFC-S
3.5.1.2 FIFO full condition in send channels
Due to the limited number of registers in the HFC-S the driver software must maintain a list of frame
start and end addresses to calculate actual FIFO depth and check FIFO full condition. Because there
are a maximum of 32 frame counter values and the start address of a frame is the incremented value
of the last frame end address the memory table must have only 32 values of 16 bits (13 bits) instead
of 64.
Remember that an increment of Z-value 1FFFh is 0200h in the B-channels!
There are two different FIFO full conditions. The first one is met when the FIFO contents comes up
to 31 frames (B-channel) or 15 frames (D-channel). There is no possibility for the HFC-S to manage
more frames even if the frames are very small.
The second limitation is the depth of the FIFO which is 512 byte for the D-channel and 7.5 KByte for
the B-channel (32KByte external RAM).
3.5.1.3 Receive Channels (B1, B2 and D reiceive)
The receive channels receive data from the S/T or PCM30 bus interface read registers. The data is
converted from HDLC into plain data and send to the FIFO. The data can then be read via the
processor interface.
The HFC-S checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does
not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is
converted by the HFC-S into plain data. After the ending flag of a frame the HFC-S checks the
HDLC CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the
FIFO named STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct
CRC field at the end of the frame.
Figure 4: FIFO Data Organisation
March 1997
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