HFC-S Cologne Chip AG, HFC-S Datasheet - Page 32

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Name
B1_D
B2_D
AUX1_D
AUX2_D
If the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots
AUX1_SSL and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots.
This is useful for an internal connection between two CODECs.
Name
MST_MODE (2Eh) 0
The pulse shape and polarity of the codec signals F1_A and F1_B is the same as the pulseshape of
the F0IO signals. The polatity of C2O can be changed by bit 1.
RESET sets register MST_MODE to all '0's.
note!
(28h)
(29h)
(2Ah)
(2Bh)
Bits
0..7
Bits
1
2
3
5, 4
7, 6
r/w
r/w
r/w
w
w
w
w
w
w
Function
read/write data registers for selected timeslot data
Function
PCM30 bus mode
'0'
'1'
polarity of C4- and C2O-clock
'0'
'1'
polarity of F0-signal
'0'
'1'
duration of F0-signal
'0'
'1'
time slot for codec-A signal F1_A
'00'
'01'
'10'
'11'
time slot for codec-B signal F1_B
'00'
'01'
'10'
'11'
slave (reset default) (C4IO and F0IO are inputs)
master (C4IO and F0IO are outputs)
F0IO is sampled on negative clock transition
F0IO is sampled on positive clock transition
F0 positive pulse (reset default)
F0 negative pulse
F0 active for one C4-clock (244ns) (reset default)
F0 active for two C4-clocks (488ns)
B1 receive slot
B2 receive slot
AUX1 receive slot
signal C2O -> pin F1_A (C2O is 2048kHz clock)
B1 receive slot
B2 receive slot
AUX1 receive slot
AUX2 receive slot
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HFC-S