HFC-S Cologne Chip AG, HFC-S Datasheet - Page 3

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

HFC-S
7 S/T interface circuitry ....................................................................................................................................44
7.1 External receiver circuitry ............................................................................................................................. 44
7.2 External transmitter circuitry ......................................................................................................................... 45
7.3 Oscillator circuitry .........................................................................................................................................47
8 State matrices for NT and TE........................................................................................................................48
8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT ................................................... 48
8.2 Activation/deactivation layer 1 for finite state matrix for TE ........................................................................49
9 Binary organisation of the frame ..................................................................................................................50
10 Clock synchronisation ..................................................................................................................................51
10.1 Clock synchronisation in NT-mode ............................................................................................................. 51
10.2 Clock synchronisation in TE-mode ............................................................................................................. 52
11 HFC-S package dimensions .........................................................................................................................53
12 ISDN PC card sample circuitry with HFC-S ..............................................................................................54
Figures
Figure 1: HFC-S block diagram ........................................................................................................................... 5
Figure 2: Pin Connection......................................................................................................................................6
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel) .................................................... 21
Figure 4: FIFO Data Organisation..................................................................................................................... 22
Figure 5: Timing relations and delayed BUSY....................................................................................................26
Figure 6: Function of IOCHRDY ........................................................................................................................ 27
Figure 7: Function of the CONNECT register bits 0..2 ...................................................................................... 33
Figure 8: PCM30 bus clock and data alignment ................................................................................................ 42
Figure 9: External receiver circuitry................................................................................................................... 44
Figure 10: External transmitter circuitry............................................................................................................ 45
Figure 11: Oscillator Circuitry ........................................................................................................................... 47
Figure 12: Frame structure at reference point S and T ...................................................................................... 50
Figure 13: Clock synchronisation in NT-mode ...................................................................................................51
Figure 14: Clock synchronisation in TE-mode ...................................................................................................52
Figure 15: HFC-S package dimensions .............................................................................................................. 53
Tables
Table 1: Selected I/O address after reset ............................................................................................................ 12
Table 2: DMA access in processor mode ............................................................................................................ 15
Table 3: SRAM size and FIFO depth................................................................................................................... 25
Table 4: S/T module part numbers and manufacturer ........................................................................................ 46
Table 5: Activation/deactivation layer 1 for finite state matrix for NT ............................................................... 48
Table 6: Activation/deactivation layer 1 for finite state matrix for TE................................................................ 49
Timing Diagrams
Timing Diagram 1: ISA-PC bus or processor access.......................................................................................... 40
Timing Diagram 2: SRAM access ....................................................................................................................... 41
Timing Diagram 3: PCM30 timing ..................................................................................................................... 42
March 1997
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