HFC-S Cologne Chip AG, HFC-S Datasheet - Page 41

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

6.2
Timing Diagram 2: SRAM access
March 1997
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
LOW
HIGH
CLK
SRA
SRAH
SRD
SRDH
SRDSU
SRDHR
SRWR
SRWRH
SRWRA
CLK
f
CLK
*)
*)
*)
/ f
SRAM access
Clock should be symmetrical so t
CLK
Clock frequency
Relative Clock frequency deviation
Clock Low Level Width
Clock High Level Width
Clock Cycle Time
Address Stable after Clock
Address Stable Hold Time after Clock
Data Out Stable after Clock
Data Out Stable Hold Time after Clock
Data In Setup Time to Clock
Data In Hold Time after Clock
Delay Time Clock
Delay Time Clock
Data and Address Hold Time after /SRWR
CHARACTERISTICS
to /SRWR Low
to /SRWR High
LOW
= t
HIGH
7.68MHz
1/ f
MIN.
30ns
30ns
15ns
20ns
5ns
5ns
5ns
0ns
2ns
5ns
1ns
0
CLK
12.288MHz
MAX.
70ns
50ns
40ns
40ns
10
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