HFC-S Cologne Chip AG, HFC-S Datasheet - Page 35

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Name
CTMT
INT_M1
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits t o '0'.
INT_M2
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'.
(19h)
(1Ah)
(1Bh)
Bits
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
r/w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Function
ignored
reset timer/WD
'1'
The bit is automatically cleared.
interrupt mask for channel B1 in transmit direction
interrupt mask for channel B2 in transmit direction
interrupt mask for channel D in transmit direction
interrupt mask for channel B1 in receive direction
interrupt mask for channel B2 in receive direction
interrupt mask for channel D in receive direction
interrupt mask for state change of TE/NT state machine
interrupt mask for timer
interrupt mask for BUSY/NOBUSY transition
must be '0'
in 64 kbit/s mode: must be '0'
in 56 kbit/s mode: value of the LSB in 7-bit mode
enable for interrupt output ('1' = enable)
56 kbit/s mode selection bit for B1-channel
'0'
'1'
56 kbit/s mode selection bit for B2-channel
'0'
'1'
'1'
'0'
'1'
'0'
reset timer/WD
64 kbit/s mode (reset default)
56 kbit/s mode
64 kbit/s mode (reset default)
56 kbit/s mode
Data inverted for B1-channel
Data not inverted for B1-channel (reset default)
Data inverted for B2-channel
Data not inverted for B2-channel (reset default)
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HFC-S